TY72011 查看數據表（PDF） - ON Semiconductor

零件编号

产品描述 (功能)

生产厂家

TY72011

Single Ended PWM Controller Featuring QR Operation and Soft Frequency Foldback

ON Semiconductor 

TY72011AP2

6.500

4.500

2.500

1.5 V

Regulation Area

FB

Virtual Point

500.0 M

OCP Condition

Error Flag

1.000 M 3.000 M 5.000 M 7.000 M 9.000 M

Figure 8.

As soon as the system recovers from the error, e.g. FB is

back within its regulation area, the IC operation comes back

to normal.

To avoid any system thermal runaway, another internal

8 x 128 ms delay is combined with the previous 128 ms. It

works as follow: the 128 ms delay is provided to account for

any normal transients that engender a temporary loss of

feedback (FB goes toward ground). However, when the

128 ms period is actually over (the feedback is definitively

lost) the IC stops the output driving pulses for a typical

period of 8 x 128 ms. During this mode, the rest of the

functions are still activated. For instance, in lack of pulses,

the self-supplied being no longer provided, the start-up

source turns on and off (when reaching the corresponding

UVLOL and UVLOH levels), creating an hiccup waveform

on the Vcc line. As soon as the feedback condition is

restored, the 8 x 128 ms is interrupted and, in synchronism

with the Vcc line, the IC is back to normal. The following

diagrams show how this mechanism takes place when FB is

down to zero (optocoupler opened) or up to Vcc

(optocoupler shorted). If we assume that the error is

permanently present, then a burst mode takes place with a

128/8 x 128 = 12.5% duty-cycle. The real transmitted

power is thus:

PoutBURST + 12Ă ·ĂLpĂ·ĂIp2Ă·ĂFswĂ·ĂDutyBURST

Over Voltage Conditions (OVP) are detected by

monitoring the Vcc level. As Figure 9 describes, three 10 V

zener plus one 5.0 V zener are connected in series together

with a 18 kW to ground. As soon as Vcc exceeds 40 V

typical, a current starts to flow in the 18 k resistor. When the

voltage developed across this element exceeds 2.5 V, an

error is triggered and immediately latches the IC off. In lack

of switching pulses, the Vcc capacitor is no longer refreshed

by the auxiliary supply and slowly discharges toward

ground. When the Vcc level crosses UVLOL, a new startup

sequence occurs. If the OVP has gone, normal IC operation

takes place. For different OVP levels, the comparator input

is accessible through pin 6.

Latched

OVP

2

7

1

+

2.5 V

VCC

6

5V

5

10 V

4

10 V

3

10 V

2k 8

18 k

OVP

Figure 9.

http://onsemi.com

11

Free Datasheet http://www.datasheet-pdf.com/

Share Link: