BU-61582 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

BU-61582

SPACE LEVEL MIL-STD-1553 BC/RT/MT ADVANCED COMMUNICATION ENGINE (SP’ACE) TERMINAL

Unspecified 

FUNCTIONAL OVERVIEW

TRANSCEIVERS

For the +5 V and -15 V/-12 V front end, the BU-61582X1(X2)

uses low-power bipolar analog monolithic and thin-film hybrid

technology. The transceiver requires +5 V and -15 V (-12 V) only

(requiring no +15 V/+12 V) and includes voltage source trans-

mitters. The voltage source transmitters provide superior line

driving capability for long cables and heavy amounts of bus load-

ing.

The receiver sections of the BU-61582 are fully compliant

with MIL-STD-1553B in terms of front end overvoltage pro-

tection, threshold, common mode rejection, and word error

rate. In addition, the receiver filters have been designed for

optimal operation with the J-Rad chip’s Manchester II

decoders.

J-RAD DIGITAL MONOLITHIC

The J-Rad digital monolithic represents the cornerstone element

of the BU-61582 SP’ACE family of terminals. The J-Rad chip is

actually a radiation hardened version of DDC’s J’ (J-prime)

monolithic which is the key building block behind DDC’s non-radi-

ation hardened BU-61580 ACE series of terminals. As such, the

J-Rad possesses all the enhanced hardware and software fea-

tures which have made the BU-61580 ACE the industry standard

1553 interface component.

The J-Rad chip consists of a dual encoder/decoder, complete

protocol for Bus Controller (BC), 1553A/B/McAir Remote

Terminal (RT), and Monitor (MT) modes; memory management

and interrupt logic; a flexible, buffered interface to a host proces-

sor bus and optional external RAM; and a separate buffered

interface to external RAM. Reference the region within the dotted

line of FIGURE 1. Besides realizing all the protocol, memory

management, and interface functions of the earlier AIM-HY

series, the J-Rad chip includes a large number of enhancements

to facilitate hardware and software design, and to further off-load

the 1553 terminal’s host processor.

DECODERS

The default mode of operation for the BU-61582 BC/RT/MT

requires a 16 MHz clock input. If needed, a software program-

mable option allows the device to be operated from a 12 MHz

clock input. Most current 1553 decoders sample using a 10 MHz

or 12 MHz clock. In the 16 MHz mode (default following a hard-

ware or software reset), the decoders sample 1553 serial data

using the 16 MHz clock. In the 12 MHz mode (or 16 MHz), the

decoders can be programmed to sample using both clock edges;

this provides a sampling rate of 24 MHz. The faster sampling rate

for the J-Rad’s Manchester II decoders provides superior per-

formance in terms of bit error rate and zero-crossing distortion

tolerance.

For interfacing to fiber optic transceivers for MIL-STD-1773

applications, a transceiverless version of the SP’ACE can be

used. These versions provide a register programmable option for

a direct interface to the single-ended outputs of a fiber optic

receiver. No external logic is needed.

TIME TAGGING

The SP’ACE includes an internal read/writable Time Tag

Register. This register is a CPU read/writable 16-bit counter with

a programmable resolution of either 2, 4, 8, 16, 32, or 64 µs per

LSB. Also, the Time Tag Register may be clocked from an exter-

nal oscillator. Another option allows software controlled incre-

menting of the Time Tag Register. This supports self-test for the

Time Tag Register. For each message processed, the value of

the Time Tag register is loaded into the second location of the

respective descriptor stack entry (“TIME TAG WORD”) for both

BC and RT modes.

Additional provided options will: clear the Time Tag Register fol-

lowing a Synchronize (without data) mode command or load the

Time Tag Register following a Synchronize (with data) mode

command; enable an interrupt request and a bit setting in the

Interrupt Status Register when the Time Tag Register rolls over

from FFFF to 0000. Assuming the Time Tag Register is not

loaded or reset, this will occur at approximately 4 second time

intervals, for 64 µs/LSB resolution, down to 131 ms intervals,

for 2 µs/LSB resolution.

Another programmable option for RT mode is the automatic clear-

ing of the Service Request Status Word bit following the

BU-61582’s response to a Transmit Vector Word mode command.

INTERRUPTS

The SP’ACE series components provide many programmable

options for interrupt generation and handling. The interrupt out-

put pin INT has three software programmable modes of opera-

tion: a pulse, a level output cleared under software control, or a

level output automatically cleared following a read of the

Interrupt Status Register. Individual interrupts are enabled by the

Interrupt Mask Register. The host processor may easily deter-

mine the cause of the interrupt by using the Interrupt Status

Register. The Interrupt Status Register provides the current state

of the interrupt conditions. The Interrupt Status Register may be

updated in two ways. In the standard interrupt handling mode, a

particular bit in the Interrupt Status Register will be updated only

if the condition exists and the corresponding bit in the Interrupt

Mask Register is enabled. In the enhanced interrupt handling

mode, a particular bit in the Interrupt Status Register will be

updated if the condition exists regardless of the contents of the

corresponding Interrupt Mask Register bit. In any case, the

respective Interrupt Mask Register bit enables an interrupt for a

particular condition.

Data Device Corporation

www.ddc-web.com

5

BU-61582

M-08/04-0

Share Link: