BU-61582 查看數據表（PDF） - Unspecified
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BU-61582 Datasheet PDF : 48 Pages
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ADDRESSING, INTERNAL REGISTERS, AND MEMORY
MANAGEMENT
The software interface of the BU-61582 to the host processor
consists of 17 internal operational registers for normal operation,
an additional 8 test registers, plus 64K X 16 of shared memory
address space. The BU-61582’s 16K X 16 of internal RAM
resides in this address space. Reference TABLE 4.
Definition of the address mapping and accessibility for the
SP’ACE’s 17 nontest registers, and the test registers, is as fol-
lows:
Interrupt Mask Register:
Used to enable and disable interrupt requests for various condi-
tions.
Configuration Registers #1 and #2:
Used to select the BU-61582’s mode of operation, and for soft-
ware control of RT Status Word bits, Active Memory Area, BC
Stop-on-Error, RT Memory Management mode selection, and
control of the Time Tag operation.
Start/Reset Register:
Used for “command” type functions, such as software reset,
BC/MT Start, Interrupt Reset, Time Tag Reset, and Time Tag
Register Test. The Start/Reset Register includes provisions for
stopping the BC in its auto-repeat mode, either at the end of the
current message or at the end of the current BC frame.
BC/RT Command Stack Pointer Register:
Allows the host CPU to determine the pointer location for the cur-
rent or most recent message when the BU-61582 is in BC or RT
modes.
BC Control Word/RT Subaddress Control Word
Register:
In BC mode, allows host access to the current or most recent BC
Control Word. The BC Control Word contains bits that select the
active bus and message format, enable off-line self-test, mask-
ing of Status Word bits, enable retries and interrupts, and speci-
fy MIL-STD-1553A or -1553B error handling. In RT mode, this
register allows host access to the current or most recent
Subaddress Control Word. The Subaddress Control Word is
used to select the memory management scheme and enable
interrupts for the current message. The read/write accessibility
can be used as an aid for testing the SP’ACE hybrid.
Time Tag Register:
Maintains the value of a real-time clock. The resolution of this
register is programmable from among 2, 4, 8, 16, 32, and 64
µs/LSB. The TAG_CLK input signal also may cause an external
TABLE 4. ADDRESS MAPPING
ADDRESS LINES
REGISTER
DESCRIPTION/ACCESSIBILITY
HEX A4 A3 A2 A1 A0
00 0 0 0 0 0 Interrupt Mask Register (RD/WR)
01 0 0 0 0 1 Configuration Register #1 (RD/WR)
02 0 0 0 1 0 Configuration Register #2 (RD/WR)
03 0 0 0 1 1 Start/Reset Register (WR)
03
0
0
0
1
1
BC/RT Command Stack Pointer Register
(RD)
04
0
0
1
0
0
BC Control Word/RT Subaddress Control
Word Register (RD/WR)
05 0 0 1 0 1 Time Tag Register (RD/WR)
06 0 0 1 1 0 Interrupt Status Register (RD)
07 0 0 1 1 1 Configuration Register #3 (RD/WR)
08 0 1 0 0 0 Configuration Register #4 (RD/WR)
09 0 1 0 0 1 Configuration Register #5 (RD/WR)
0A 0 1 0 1 0 Data Stack Address Register (RD/WR)
0B
0
1
0
1
1
BC Frame Time Remaining Register
(RD/WR)
0C
0
1
1
0
0
BC Time Remaining to Next Message
Register (RD/WR)
0D
0
1
1
0
1
BC Frame Time/RT Last Command
/MT Trigger Word Register (RD/WR)
0E 0 1 1 1 0 RT Status Word Register (RD)
0F 0 1 1 1 1 RT BIT Word Register (RD)
10 1 0 0 0 0 Test Mode Register 0
•
•
17 1 0 1 1 1 Test Mode Register 7
18 1 1 0 0 0 reserved
•
•
1F 1 1 1 1 1 reserved
oscillator to clock the Time Tag Register. Start-of-Message
(SOM) and End-of-Message (EOM) sequences in BC, RT, and
Message Monitor modes cause a write of the current value of
the Time Tag Register to the stack area of RAM.
Interrupt Status Register:
Mirrors the Interrupt Mask Register and contains a Master
Interrupt bit. It allows the host processor to determine the cause
of an interrupt request by means of a single READ operation.
Data Device Corporation
www.ddc-web.com
7
BU-61582
M-08/04-0
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