MAX19708ETM 查看數據表（PDF） - Maxim Integrated
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MAX19708ETM Datasheet PDF : 37 Pages
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10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 11MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33µF, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution
N
Integral Nonlinearity
INL
CONDITIONS
MIN TYP MAX UNITS
12
Bits
±1.25
LSB
Differential Nonlinearity
DNL
Guaranteed monotonic over codes 100 to
4000 (Note 2)
-1.0 ±0.65 +1.2
LSB
Gain Error
GE
Zero-Code Error
ZE
Output-Voltage Low
VOL
Output-Voltage High
VOH
DC Output Impedance
Settling Time
Glitch Impulse
Rx ADC-Tx DAC TIMING CHARACTERISTICS
RL > 200kΩ
RL > 200kΩ
RL > 200kΩ
DC output at midscale
From 1/4 FS to 3/4 FS, within ±10 LSB
From 0 to FS transition
±0.7
%FS
±0.6
%FS
0.1
V
2.56
V
4
Ω
1
µs
24
nV•s
CLK Rise to Channel-I Output Data
Valid
tDOI
Figure 3 (Note 2)
5.3
7.0
8.5
ns
CLK Fall to Channel-Q Output
Data Valid
tDOQ Figure 3 (Note 2)
6.8
9.1 11.3
ns
I-DAC DATA to CLK Fall Setup
Time
tDSI
Figure 6 (Note 2)
10
ns
Q-DAC DATA to CLK Rise Setup
Time
CLK Fall to I-DAC Data Hold Time
CLK Rise to Q-DAC Data Hold
Time
tDSQ
tDHI
tDHQ
Figure 6 (Note 2)
Figure 6 (Note 2)
Figure 6 (Note 2)
10
ns
0
ns
0
ns
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 7, Note 2)
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to CS Setup Time
CS High Pulse Width
CS High to DOUT Active High
tDS
tDH
tCH
tCL
tCP
tCS
tCSW
tCSD
Bit AD0 set
50
%
±15
%
2.5
ns
10
ns
10
ns
0
ns
25
ns
25
ns
50
ns
10
ns
80
ns
200
ns
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