AD8177ABPZ 查看數據表（PDF） - Analog Devices
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AD8177ABPZ Datasheet PDF : 40 Pages
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TIMING CHARACTERISTICS (SERIAL MODE)
Table 2.
Parameter
Serial Data Setup Time
CLK Pulse Width
Serial Data Hold Time
CLK Pulse Separation
CLK to UPDATE Delay
UPDATE Pulse Width
CLK to SEROUT Valid
Propagation Delay, UPDATE to Switch On
Data Load Time, CLK = 5 MHz, Serial Mode
RST Time
Symbol
t1
t2
t3
t4
t5
t6
t7
AD8177
Limit
Min
Typ
Max
Unit
40
ns
60
ns
50
ns
140
ns
10
ns
90
ns
120
ns
80
ns
9
μs
140
200
ns
1
CLK
0
1
SERIN
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
1
SEROUT
0
t2
t1
t3
OUT4 (D4)
t7
Table 3. Logic Levels, VDD = 3.3 V
VIH
VIL
VOH
SER/PAR, CLK, SER/PAR, CLK, SEROUT
SERIN, UPDATE SERIN, UPDATE
2.0 V min
0.6 V max
2.8 V min
t4
LOAD DATA INTO
SERIAL REGISTER
ON FALLING EDGE
OUT4 (D3)
OUT0 (D0)
t5
t6
TRANSFER DATA FROM SERIAL
REGISTER TO PARALLEL
LATCHES DURING LOW LEVEL
Figure 2. Timing Diagram, Serial Mode
VOL
SEROUT
0.4 V max
IIH
SER/PAR, CLK,
SERIN, UPDATE
20 μA max
IIL
SER/PAR, CLK,
SERIN, UPDATE
–20 μA max
IOH
SEROUT
–1 mA min
IOL
SEROUT
1 mA min
Table 4. H and V Logic Levels, VDD = 3.3 V
VOH
VOL
2.7 V min
0.5 V max
IOH
–3 mA max
IOL
3 mA max
Table 5. RST Logic Levels, VDD = 3.3 V
VIH
VIL
2.0 V min
0.6 V max
Table 6. CS Logic Levels, VDD = 3.3 V
VOH
VOL
2.0 V min
0.6 V max
IIH
−60 μA max
IIH
100 μA max
IIL
−120 μA max
IOL
40 μA max
Rev. 0 | Page 5 of 40
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