AD8177ABPZ 查看數據表（PDF） - Analog Devices
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AD8177ABPZ Datasheet PDF : 40 Pages
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AD8177
TIMING CHARACTERISTICS (PARALLEL MODE)
Table 7.
Parameter
Parallel Data Setup Time
WE Pulse Width
Parallel Hold Time
WE Pulse Separation
WE to UPDATE Delay
UPDATE Pulse Width
Propagation Delay, UPDATE to Switch On
RST Time
Symbol
t1
t2
t3
t4
t5
t6
Limit
Min
Typ
Max
Unit
80
ns
110
ns
150
ns
90
ns
10
ns
90
ns
80
ns
140
200
ns
1
WE
0
1
D0 TO D4
A0 TO A2
0
1 = LATCHED
UPDATE
0 = TRANSPARENT
t2
t1
t3
Table 8. Logic Levels, VDD = 3.3 V
VIH
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
UPDATE
VIL
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
UPDATE
VOH
SEROUT
2.0 V min
0.6 V max
Disabled
t4
t5
t6
Figure 3. Timing Diagram, Parallel Mode
VOL
SEROUT
Disabled
IIH
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
UPDATE
20 μA max
IIL
SER/PAR, WE,
D0, D1, D2, D3,
D4, A0, A1, A2,
UPDATE
−20 μA max
IOH
SEROUT
Disabled
IOL
SEROUT
Disabled
Table 9. H and V Logic Levels, VDD = 3.3 V
VOH
VOL
2.7 V min
0.5 V max
IOH
–3 mA max
IOL
3 mA max
Table 10. RST Logic Levels, VDD = 3.3 V
VIH
VIL
2.0 V min
0.6 V max
IIH
−60 μA max
IIL
−120 μA max
Table 11. CS Logic Levels, VDD = 3.3 V
VOH
VOL
2.0 V min
0.6 V max
IIH
100 μA max
IOL
40 μA max
Rev. 0 | Page 6 of 40
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