AD8117 查看數據表（PDF） - Analog Devices

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AD8117

600 MHz, 32 × 32 Buffered, Analog Crosspoint Switch

Analog Devices 

Data Sheet

AD8117/AD8118

TIMING CHARACTERISTICS (SERIAL MODE)

Specifications subject to change without notice.

Table 2.

Parameter

Serial Data Setup Time

CLK Pulse Width

Serial Data Hold Time

CLK Pulse Separation

CLK to UPDATE Delay

UPDATE Pulse Width

CLK to DATA OUT Valid

Propagation Delay, UPDATE to Switch On or Off

RESET Pulse Width

RESET Time

Symbol

t1

t2

t3

t4

t5

t6

t7

Limit

Min

Typ

Max

Unit

40

ns

50

ns

50

ns

150

ns

10

ns

90

ns

120

ns

100

ns

60

ns

200

ns

1

WE

0

1

CLK

0

1

DATA IN

0

1 = LATCHED

UPDATE

0 = TRANSPARENT

DATA OUT

t2

t1

t3

OUT31 (D5)

t7

t4

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

OUT30 (D4)

OUT00 (D0)

t5

t6

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

Table 3. Logic Levels

VIH

VIL

RESET,

SER/PAR, CLK,

DATA IN,

UPDATE

RESET,

SER/PAR, CLK,

DATA IN,

UPDATE

2.0 V min

0.6 V max

1 See Figure 15.

Figure 2. Timing Diagram, Serial Mode

VOH

DATA OUT

VOL

DATA OUT

VDD − 0.3 V min DGND + 0.5 V max

IIH

RESET1,

SER/PAR, CLK,

DATA IN,

UPDATE

1 μA max

IIL

RESET1,

SER/PAR, CLK,

DATA IN,

UPDATE

–1 μA min

IOH

DATA OUT

−1 mA max

IOL

DATA OUT

1 mA min

Rev. B | Page 5 of 36

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