AD8117 查看數據表（PDF） - Analog Devices

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AD8117

600 MHz, 32 × 32 Buffered, Analog Crosspoint Switch

Analog Devices 

AD8117/AD8118

Data Sheet

TIMING CHARACTERISTICS (PARALLEL MODE)

Specifications subject to change without notice.

Table 4.

Parameter

Parallel Data Setup Time

WE Pulse Width

Parallel Data Hold Time

WE Pulse Separation

WE to UPDATE Delay

UPDATE Pulse Width

Propagation Delay, UPDATE to Switch On or Off

RESET Pulse Width

RESET Time

Symbol

t1

t2

t3

t4

t5

t6

Limit

Min

Typ

Max

Unit

80

ns

110

ns

150

ns

90

ns

10

ns

90

ns

100

ns

60

ns

200

ns

1

WE

0

1

D0 TO D5

A0 TO A4

0

1 = LATCHED

UPDATE

0 = TRANSPARENT

t2

t1

t3

Table 5. Logic Levels

VIH

VIL

RESET,

SER/PAR, WE,

D0, D1, D2, D3,

D4, D5, A0, A1,

A2, A3, A4,

UPDATE

RESET,

SER/PAR, WE,

D0, D1, D2, D3,

D4, D5, A0, A1,

A2, A3, A4,

UPDATE

2.0 V min

0.6 V max

VOH

DATA OUT

Disabled

1 See Figure 15.

t4

t5

t6

Figure 3. Timing Diagram, Parallel Mode

VOL

DATA OUT

Disabled

IIH

RESET1,

SER/PAR, WE,

D0, D1, D2, D3,

D4, D5, A0, A1,

A2, A3, A4,

UPDATE

1 μA max

IIL

RESET1,

SER/PAR, WE,

D0, D1, D2, D3,

D4, D5, A0, A1,

A2, A3, A4,

UPDATE

–1 μA min

IOH

DATA OUT

Disabled

IOL

DATA OUT

Disabled

Rev. B | Page 6 of 36

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