AD8104(2016) 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

AD8104
(Rev.:2016)

600 MHz, 32 × 16 Buffered Analog Crosspoint Switch

Analog Devices 

Data Sheet

TIMING CHARACTERISTICS (SERIAL MODE)

Specifications subject to change without notice.

Table 2.

Parameter

Serial Data Setup Time

CLK Pulse Width

Serial Data Hold Time

CLK Pulse Separation

CLK to UPDATE Delay

UPDATE Pulse Width

CLK to DATA OUT Valid

Propagation Delay, UPDATE to Switch On or Off

RESET Pulse Width

RESET Time

Symbol

t1

t2

t3

t4

t5

t6

t7

AD8104/AD8105

Limit

Min

Typ

Max

Unit

40

ns

50

ns

50

ns

150

ns

10

ns

90

ns

120

ns

100

ns

60

ns

200

ns

1

WE

0

1

CLK

0

1

DATA IN

0

1 = LATCHED

UPDATE

0 = TRANSPARENT

1

DATA OUT

0

t2

t1

t3

OUT15 (D5)

t7

t4

LOAD DATA INTO

SERIAL REGISTER

ON FALLING EDGE

OUT15 (D4)

OUT0 (D0)

t5

t6

TRANSFER DATA FROM SERIAL

REGISTER TO PARALLEL

LATCHES DURING LOW LEVEL

Figure 2. Timing Diagram, Serial Mode

Table 3. Logic Levels

VIH

VIL

RESET,

SER/PAR, CLK,

DATA IN,

UPDATE

RESET,

SER/PAR, CLK,

DATA IN,

UPDATE

2.0 V min

0.6 V max

VOH

DATA OUT

VOL

DATA OUT

IIH

RESET1,

SER/PAR, CLK,

DATA IN, UPDATE

VDD − 0.3 V DGND +

min

0.5 V max

1 μA max

IIL

RESET1,

SER/PAR, CLK,

DATA IN, UPDATE

IOH

DATA OUT

IOL

DATA OUT

–1 μA min

−1 mA max 1 mA min

1 See Figure 15.

Rev. A | Page 5 of 36

Share Link: