AD8104 查看數據表（PDF） - Analog Devices

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AD8104

600 MHz, 32 × 16 Buffered Analog Crosspoint Switch

Analog Devices 

TRUTH TABLE AND LOGIC DIAGRAM

Table 9. Operation Truth Table

WE

UPDATE CLK

X

X

X

DATA

INPUT

X

DATA

OUTPUT

X

RESET

0

1

X

Datai 1

Datai-192

1

0

X

X

1

0

X

1

X

X

1 Datai: serial data.

2 D0…D5: data bits.

3 A0…A3: address bits.

D0…D52 N/A in

1

A0…A33 parallel

mode

X

N/A in

1

parallel

mode

X

X

1

AD8104/AD8105

SER/PAR

X

0

1

X

1

Operation/Comment

Asynchronous reset. All outputs are

disabled. Remainder of logic in 192-bit shift

register is unchanged.

Serial mode. The data on the serial DATA IN

line is loaded into the serial register. The first

bit clocked into the serial register appears

at DATA OUT 192 clock cycles later.

Parallel mode. The data on parallel lines D0

to D5 are loaded into the shift register

location addressed by A0 to A3.

Switch matrix update. Data in the 192-bit

shift register transfers into the parallel

latches that control the switch array.

No change in logic.

Rev. 0 | Page 13 of 36

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