EN5394QI 查看數據表（PDF） - Altera Corporation

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EN5394QI

9A PowerSoC Voltage Mode Synchronous Buck PWM DC-DC Converter With Integrated Inductor

Altera Corporation 

Phase Delay between

S_IN and S_OUT1

Phase Delay between

S_IN and S_OUT1

Phase Delay Accuracy1

Pre-Bias Level

Non-Monotonicity

POK Lower Threshold as

a percent of VOUT3

POK Upper Threshold as

a percent of VOUT3

POK Falling Edge

Deglitch Delay4

POK Output Low Voltage

POK Output High Voltage

Ternary Pin Logic Low5

Ternary Pin Logic High5

Ternary Pin Input Current

(see Figure 5)5

Binary Input Logic Low

Threshold6

Binary Input Logic High

Threshold6

ΦDEL

ΦDEL

VPB

VPB_NM

POKLT

POKUT

VPOKL

VPOKH

VT-Low

VT-High

ITERN

VB-Low

VB-High

EN5394QI

Phase delay programmable via

resistor connected from S_Delay 20

150

ns

to AGND.

Delay By-Pass Mode

(MAR1 floating, MAR2 high)

10

ns

-20

20

%

Allowable Pre-Bias as a fraction

of programmed output voltage

20

85

%

(subject to a minimum of 300mV)

Allowable non monotonicity

50

mV

VOUT rising

VOUT falling

92

90

%

VOUT rising

VOUT falling

120

115

%

60

µs

With 4mA current sink into POK

2.375V ≤ VIN ≤ 6.6V

Tie pin to GND

Pull up to VIN through an external

resistor REXT – see Figure 5.

VIN = 2.375V, REXT = 3.32kΩ

VIN = 3.3V, REXT = 15kΩ

VIN = 5.0V, REXT = 24.9kΩ

VIN = 6.6V, REXT = 49.9kΩ

0.4

V

VIN

V

0

V

see Input

Current

below

50

70

100

µA

85

0.8

1.8

NOTES:

1. Parameter guaranteed by design.

2. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.

3. POK threshold when VOUT is rising is nominally 92%. This threshold is 90% when VOUT is falling. After crossing the

90% level, there is a 256 clock cycle (~50us) delay before POK is de-asserted. The 90%, 92%, 115%, and 120%

levels are nominal values. Expect these thresholds to vary by ±3%.

4. On the falling edge of VOUT below 90% of programmed value, POK response is delayed for the duration of the

deglitch delay time. Any VOUT glitch shorter than the deglitch time is ignored.

5. M/S, MAR1, and MAR2 are ternary. Ternary pins have three logic levels: high, float, and low. These pins are only

meant to be strapped to VIN through an external resistor, strapped to GND, or left floating. Their state cannot be

changed while the device is on.

6. Binary input pins are EN_PB and OCP_ADJ.

03738

6

October 11, 2013

www.altera.com/enpirion

Rev E

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