Figure 1-1. Block Diagram with Typical Circuit, Period Group Control 0 to 100%
C2
2.2 µF/
10 V
R4
100 kΩ
R5
12 kΩ
max
100 kΩ
min
R6
18 kΩ
L
D1
220 kΩ
(250 V~)
R2
R1
(Rsync)
18 kΩ/
2W
Load
1000 W
2
8
1
Ramp
generator
Synchronization
-VS
5
Supply
7
GND
C1
100 µF/
16 V
VM = 230 V~
MT2
3
+
4+
Full-wave logic
- Comparator
6
Pulse
amplifier
100 Ω
R3
MT1
Reference voltage
1.4 V
T2117
N
2. Pin Configuration
Figure 2-1. Pinning DIP8/SO8
RAMP 1
8 VSYNC
CRAMP 2
POSIN 3
T2117
7 GND
6 OUTPUT
NEGIN 4
5 VS
Table 2-1.
Pin
1
2
3
4
5
6
7
8
Pin Description
Symbol Function
RAMP Ramp output
CRAMP Ramp capacitor
POSIN Non-inverting comparator input
NEGIN Inverting comparator input
VS
Supply voltage
OUTPUT Trigger pulse output
GND
Ground
VSYNC Voltage synchronization
2 T2117
4768B–INDCO–10/05