320724-01 查看數據表（PDF） - National Instruments Corporation
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320724-01 Datasheet PDF : 16 Pages
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TNT4882
Single-Chip IEEE 488.2 Talker/Listener ASIC
Generic Pin Configuration
NDACN
NRFDN
GND
DAVN
EOIN
GND
VDD
DIO4N
DIO3N
GND
DIO2N
DIO1N
GND
VDD
XTAL0
XTAL1
GND
KEYCLKN
KEYDQ
KEYRSTN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
81
50
82
49
83
48
84
47
85
46
86
45
87
44
88
43
89
42
90
TNT4882
41
91
Generic Pin Configuration
40
92
39
93
38
94
37
95
36
96
35
97
34
98
33
99
32
100
31
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
DATA7
DATA6
GND
DATA5
DATA4
GND
DATA3
DATA2
DATA1
GND
VDD
DATA0
RDY1
GND
VDD
GND
INTR
DACKN
DRQ
BURST_RDN
Figure 3. TNT4882 Generic Pin Configuration
Generic Pin Description
All pins with names that end in ‘N’ are active low; all others are active high. All input (I) and bidirectional (I/O) pins have an internal pull-up
resistor between 50 kΩ and 150 kΩ.
Note: You can also see the “Hardware Considerations” chapter of the “TNT Programmer Reference Manual” (P/N 320724-01) for more
information.
Pin No.(s)
1
2,3,5,6,7,9,10,11
14
19-15
20
21
22
23
26
28
29
30
31
Name(s)
BBUS_OEN
DATA15-8
ABUSN
ADDR4-0
ABUS_OEN
TADCS
CPUACC
TRIG
PAGED
REM
SWAPN
FIFO_RDY
BURST_RDN
32
DRQ
33
DACKN
34
INTR
38
RDY1
50,49,47,46,
44,43,42,39
DATA7-0
Type Description
O
Asserts when DATA7-0 (B bus) is enabled for output
I/O Upper 8 bits of bidirectional three-state data bus for transfer of commands, data, and status
between TNT4882 and CPU – also known as the A bus
I
Enables register accesses through the A bus (DATA15-8) – DATA15 is the most significant bit
I
Determines which register to access during a read or write operation
O
Asserts when DATA15-8 (A bus) is enabled for output
O
Asserts when the TNT4882 is an active or addressed IEEE 488 Talker (TADS, TACS, or SPAS)
O
Asserts in two-chip mode during a NAT4882 register I/O access
O
Asserts when in DTAS or when the auxiliary trigger software command is issued
I
Asserting this pin pages in the page-in registers in the 7210 mode
O
Asserts when the TNT4882 is in a remote state (REMS or RWLS)
I
Rearranges the order of the registers when asserted and in 9914 mode
O
Asserts when the FIFO is ready for burst access
I
When asserted, places the TNT4882 in a burst read mode, in which the first word in the
FIFO is always driven on the TNT4882 data bus – words are removed from the FIFOs at
each rising edge of RDN – see reference manual for details
O
Asserts to request a DMA transfer cycle
I
Enables FIFO accesses during a DMA transfer cycle
O
Asserts when one or more of the unmasked interrupt conditions becomes true
O
Asserts during an I/O access to indicate that the read data is available or that the write
data has been latched – asserts immediately on an access to Turbo488 registers or in
one-chip mode
I/O Lower eight bits of bidirectional three-state data bus for transfer of commands, data, and
status between TNT4882 and CPU – also known as the B bus – DATA7 is the most significant bit
Table continued on page 4
National Instruments 3
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