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AZC002-02N

Low Capacitance ESD Protection Array For High Speed Data Interfaces

Amazing Microelectronic 

AZC002-02N

Low Capacitance ESD Protection Array

For High Speed Data Interfaces

Applications Information

A. Design Considerations

The ESD protection scheme for system I/O

connector is shown in the Fig. 1. In Fig. 1, the

diodes D1 and D2 are general used to protect

data line from ESD stress pulse. If the power-rail

ESD clamping circuit is not placed between VDD

and GND rails, the positive pulse ESD current

(IESD1) will pass through the ESD current path1.

Thus, the ESD clamping voltage VCL of data line

can be described as follow:

VCL = Fwd voltage drop of D1 + supply voltage of

VDD rail + L1 × d(IESD1)/dt + L2 × d(IESD1)/dt

Where L1 is the parasitic inductance of data line,

and L2 is the parasitic inductance of VDD rail.

An ESD current pulse can rise from zero to its

peak value in a very short time. As an example, a

level 4 contact discharge per the IEC61000-4-2

standard results in a current pulse that rises from

zero to 30A in 1ns. Here d(IESD1)/dt can be

approximated by ∆IESD1/∆t, or 30/(1x10-9). So

just 10nH of total parasitic inductance (L1 and L2

combined) will lead to over 300V increment in

VCL! Besides, the ESD pulse current which is

directed into the VDD rail may potentially

damage any components that are attached to

that rail. Moreover, it is common for the forward

voltage drop of discrete diodes to exceed the

damage threshold of the protected IC. This is due

to the relatively small junction area of typical

discrete components. Of course, the discrete

diode is also possible to be destroyed due to its

power dissipation capability is exceeded.

The AZC002-02N has an integrated

power-rail ESD clamped circuit between VDD

and GND rails. It can successfully overcome

previous disadvantages. During an ESD event,

the positive ESD pulse current (IESD2) will be

directed through the integrated power-rail ESD

clamped circuit to GND rail (ESD current path2).

The clamping voltage VCL on the data line is

small and protected IC will not be damaged

because power-rail ESD clamped circuit offer a

low impedance path to discharge ESD pulse

current.

power-rail ESD

clamp ing circuit

+

Vp

_

AZC002-02N

I ESD2

D1

D2

L2

I ESD1

data line

L1

VESD

+

VCL

_

VDD rail

Pr ote cte d

IC

GND rail

ESD current path 1 (I ESD1)

ESD current path 2 (I ESD2)

Fig. 1 Application of positive ESD pulse between data line and GND rail.

Revision 2011/07/30 ©2011-2012 Amazing Micro.

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