ALC5640VB 查看數據表（PDF） - Realtek Semiconductor

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ALC5640VB

Multi-Channel Audio Hub/CODEC and SounzReal Digital Sound Effect for Mobile Devices

Realtek Semiconductor 

ALC5640-VB

Datasheet

7.4. Clocking

The system clock of ALC5640 can be selected from MCLK or PLL. MCLK is always provided externally

while the reference clock of PLL can be selected from MCLK, BCLK1/2. The driver should arrange the

clock of each block and setup each divider.

The Clk_sys_i2s1=256*Fs provides clocks into stereo DAC/ADC filter that can be selected from MCLK

or PLL. Refer to Figure 5. Audio SYSCLK

The Clk_sys_i2s2=256*Fs provides clocks into mono DAC/ADC filter that can be selected from MCLK,

PLL, refer to Figure 5. Audio SYSCLK

When enable ASRC (Asynchronous Sample Rate Converter) function, the clock sources from MCLK and

BCLK1 (or BCLK2) are allowed to be asynchronous. The Realtek ASRC technology can ensure data

accuracy and keep audio performance under clock source asynchronous.

When ALC5640 at master mode, the clock source from MCLK will be divided and be sent to external

device. The ratio of BCLK and LRCK can set by register – MX-73.

MCLK

BCLK1

LRCK1

BCLK2

LRCK2

MX80[3]

÷2

MX80[15:14]

MCLK

MX80[13:12]

Inter. Clock

(Slave)

(Slave)

PLL

MX81 & MX82

PLL

MX73[14:12]

DIV_F1

Clk_sys_i2s1(256FS)

MX89[14:12]

div

ASRC1

MX83[15]

Filter_Clk1

MX73[10:8] Clk_sys_i2s2(256FS) MX89[10:8]

DIV_F2

div

ASRC2

MX83[12]

MX83[14]

Filter_Clk2

1/3

MX70[15]

MX71[15]

BCLK1(Master)

MX70[15]

LRCK1(Master)

LRCK1(Slave)

Master Mode

LRCK/BCLK

Ratio

MX73[15]

Filter_Clk1 (256FS)

BCLK2(Master)

MX71[15]

LRCK2(Master)

LRCK2(Slave)

Master Mode

LRCK/BCLK

Ratio

MX73[11]

Clk_sys_i2s2(256FS)

Stereo DAC

Filter

Stereo ADC

Filter

Mono DAC

Filter 1

Mono DAC

Filter 2

Mono ADC

Filter 1

Mono ADC

Filter 2

Figure 6. Audio Clock Tree

Multi-Channel Audio Hub/CODEC and SounzRealTM

16

Digital Sound Effect for Mobile Devices

Rev. 0.91

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