MCP3008-I 查看數據表（PDF） - Microchip Technology

零件编号

产品描述 (功能)

生产厂家

MCP3008-I

2.7V 4-Channel/8-Channel 10-Bit A/D Converters with SPI Serial Interface

Microchip Technology 

MCP3004/3008

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VREF = 5V,

TA = -40°C to +85°C, fSAMPLE = 200 ksps and fCLK = 18*fSAMPLE. Unless otherwise noted, typical values apply for

VDD = 5V, TA = +25°C.

Parameter

Sym

Min

Typ

Max Units

Conditions

Leakage Current

—

0.001

±1

µA

Switch Resistance

—

1000

—

Ω See Figure 4-1

Sample Capacitor

—

20

—

pF See Figure 4-1

Digital Input/Output

Data Coding Format

Straight Binary

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

Pin Capacitance

(All Inputs/Outputs)

Timing Parameters

VIH 0.7 VDD

—

VIL

—

VOH

4.1

—

VOL

—

—

ILI

-10

—

ILO

-10

—

CIN,

—

—

COUT

—

0.3 VDD

—

0.4

10

10

10

V

V

V IOH = -1 mA, VDD = 4.5V

V IOL = 1 mA, VDD = 4.5V

µA VIN = VSS or VDD

µA VOUT = VSS or VDD

pF VDD = 5.0V (Note 1)

TA = 25°C, f = 1 MHz

Clock Frequency

fCLK

—

—

3.6

MHz VDD = 5V (Note 3)

1.35

MHz VDD = 2.7V (Note 3)

Clock High Time

tHI

125

—

—

ns

Clock Low Time

tLO

125

—

—

ns

CS Fall To First Rising CLK Edge tSUCS

100

—

—

ns

CS Fall To Falling CLK Edge

tCSD

—

—

0

ns

Data Input Setup Time

tSU

50

—

—

ns

Data Input Hold Time

tHD

50

—

—

ns

CLK Fall To Output Data Valid

tDO

—

—

125

ns VDD = 5V, See Figure 1-2

200

ns VDD = 2.7V, See Figure 1-2

CLK Fall To Output Enable

tEN

—

—

125

ns VDD = 5V, See Figure 1-2

200

ns VDD = 2.7V, See Figure 1-2

CS Rise To Output Disable

tDIS

—

—

100

ns See Test Circuits, Figure 1-2

CS Disable Time

tCSH

270

—

—

ns

DOUT Rise Time

tR

—

—

100

ns See Test Circuits, Figure 1-2

(Note 1)

DOUT Fall Time

tF

—

—

100

ns See Test Circuits, Figure 1-2

(Note 1)

Note 1: This parameter is established by characterization and not 100% tested.

2: See graphs that relate linearity performance to VREF levels.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity

performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock

Speed”, “Maintaining Minimum Clock Speed”, for more information.

DS21295D-page 4

© 2008 Microchip Technology Inc.

Share Link: