PUSB3TB6 查看數據表（PDF） - NXP Semiconductors.
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PUSB3TB6 Datasheet PDF : 13 Pages
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NXP Semiconductors
PUSB3TB6
ESD protection for ultra high-speed interfaces
4
I
(A)
3
aaa-013508
0
I
(A)
-1
aaa-013509
2
-2
1
-3
0
0
2
4
6
VCL (V)
Fig 6.
IEC 61000-4-5; tp = 8/20 s; positive pulse
Dynamic resistance with positive clamping;
typical values
-4
-6
-4
-2
0
VCL (V)
Fig 7.
IEC 61000-4-5; tp = 8/20 s; negative pulse
Dynamic resistance with negative clamping;
typical values
14
I
(A)
12
10
8
6
aaa-013510
0
I
(A)
-2
-4
-6
-8
aaa-013511
4
-10
2
-12
0
0
4
8
12
VCL (V)
Fig 8.
tp = 100 ns; Transmission Line Pulse (TLP)
Dynamic resistance with positive clamping;
typical values
-14
-12
-8
-4
0
VCL (V)
Fig 9.
tp = 100 ns; Transmission Line Pulse (TLP)
Dynamic resistance with negative clamping;
typical values
The device uses an advanced clamping structure showing a negative dynamic resistance.
This snap-back behavior strongly reduces the clamping voltage to the system behind the
ESD protection during an ESD event. Do not connect unlimited DC current sources to the
data lines to avoid keeping the ESD protection device in snap-back state after exceeding
breakdown voltage (due to an ESD pulse for instance).
PUSB3TB6
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 19 August 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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