AD7278(RevC) 查看數據表（PDF） - Analog Devices
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AD7278 Datasheet PDF : 28 Pages
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AD7276/AD7277/AD7278
TIMING EXAMPLES
For the AD7276, if CS is brought high during the 14th SCLK rising
edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If CS is brought high during the 16th SCLK rising
edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of
2.97 MSPS is achievable. This is illustrated in the following two
timing examples.
Timing Example 1
In Figure 6, using a 14 SCLK cycle, fSCLK = 48 MHz and the
throughput is 3 MSPS. This produces a cycle time of t2 +
12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and
tACQ = 67 ns.
This satisfies the requirement of 60 ns for tACQ. Figure 6 also
shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where
t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying
the minimum requirement of 4 ns.
Timing Example 2
The example in Figure 7 uses a 16 SCLK cycle, fSCLK = 48 MHz,
and the throughput is 2.97 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and
tACQ = 70 ns. Figure 7 shows that tACQ comprises 2.5(1/fSCLK) + t8 +
tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
t1
CS
SCLK
t2
1
tCONVERT
t6
2
3
4
5
t3
SDATA
Z ZERO
THREE-
STATE 2 LEADING
ZEROS
DB11
DB10
t4
DB9
B
13
t7
DB1 DB0
1/THROUGHPUT
14
15
16
t5
t8
ZERO ZERO
2 TRAILING
ZEROS
tQUIET
THREE-STATE
Figure 5. AD7276 Serial Interface Timing Diagram
t1
CS
SCLK
t2
1
tCONVERT
t6
2
3
4
t3
t4
SDATA
Z ZERO DB11 DB10 DB9
THREE-
STATE 2 LEADING
ZEROS
5
t7
B
13
14
t5
t9
DB1
DB0
1/THROUGHPUT
tQUIET
THREE-STATE
Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
t1
CS
SCLK
tCONVERT
t2
B
1
2
3
4
5
12
13
14
15
16
t8
tQUIET
12.5(1/fSCLK)
1/THROUGHPUT
tACQUISITION
Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle
Rev. C | Page 10 of 28
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