AD7278(RevC) 查看數據表（PDF） - Analog Devices
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AD7278 Datasheet PDF : 28 Pages
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AD7276/AD7277/AD7278
Parameter
POWER REQUIREMENTS
VDD
IDD
Normal Mode (Static)
Normal Mode (Operational)
Partial Power-Down Mode (Static)
Full Power-Down Mode (Static)
Power Dissipation5
Normal Mode (Operational)
Partial Power-Down
Full Power-Down
A Grade1, 2
2.35/3.6
0.5
5.5
3.5
34
2
10
19.8
10.5
102
7.2
1 Temperature range from −40°C to +125°C.
2 Typical specifications are tested with VDD = 3 V and at 25°C.
3 See the Terminology section.
4 Guaranteed by characterization.
5 See the Power vs. Throughput Rate section.
B Grade1, 2
2.35/3.6
0.5
5.5
3.5
34
2
10
19.8
10.5
102
7.2
Unit
V min/max
mA typ
mA max
mA typ
μA typ
μA max
μA max
mW max
mW typ
μW typ
μW max
Test Conditions/Comments
Digital I/Ps = 0 V or VDD
VDD = 3.6 V, SCLK on or off
VDD = 2.35 V to 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
−40°C to +85°C, typically 0.1 μA
+85°C to +125°C
VDD = 3.6 V, fSAMPLE = 3 MSPS
VDD = 3 V
VDD = 3 V
VDD = 3.6 V, −40°C to +85°C
TIMING SPECIFICATIONS—AD7276/AD7277/AD7278
VDD = 2.35 V to 3.6 V, TA = TMIN to TMAX, unless otherwise noted.1
Table 5.
Parameter2
fSCLK 3
tCONVERT
tQUIET
Limit at TMIN, TMAX
500
48
16
14 × tSCLK
12 × tSCLK
10 × tSCLK
4
t1
t2
t3 5
t45
t5
t6
t75
t8
t9
TPOWER-UP 6
3
6
4
15
0.4 tSCLK
0.4 tSCLK
5
14
5
4.2
1
Unit
kHz min4
MHz max
MHz max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
μs max
Description
B grade
Y grade
AD7276
AD7277
AD7278
Minimum quiet time required between the bus relinquish and the
start of the next conversion
Minimum CS pulse width
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
SCLK to data valid hold time
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
CS rising edge to SDATA three-state
Power-up time from full power-down
1 Sample tested during initial release to ensure compliance. All timing specifications given are with a 10 pF load capacitance. With a load capacitance greater than this
value, a digital buffer or latch must be used.
2 Guaranteed by characterization. All input signals are specified with tr = tf = 2 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
3 Mark/space ratio for the SCLK input is 40/60 to 60/40.
4 Minimum fSCLK at which specifications are guaranteed.
5 The time required for the output to cross the VIH or VIL voltage.
6 See the Power-Up Times section.
Rev. C | Page 8 of 28
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