MB39A108 查看數據表（PDF） - Fujitsu

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MB39A108

5 ch DC/DC Converter IC with Synchronous Rectification

Fujitsu 

MB39A108

■ PIN DESCRIPTION

Block

CH1

CH2

CH3

CH4

CH5

OSC

Pin No.

PKG

Pin name I/O

Description

TSSOP BCC

36

33

FB1

O Error amplifier output terminal.

37

34

− INE1

I Error amplifier inverted input terminal.

38

35

CS1

⎯ Soft-start setting capacitor connection terminal.

34

31

OUT1-1

O

P-ch drive output terminal

(External main side FET gate driving).

33

30

OUT1-2

O

N-ch drive output terminal

(External synchronous rectification side FET gate driving).

4

40

DTC2

I Dead time control terminal.

3

39

FB2

O Error amplifier output terminal

2

38

− INE2

I Error amplifier inverted input terminal.

1

37

CS2

⎯ Soft-start setting capacitor connection terminal.

32

29

OUT2

O P-ch drive output terminal.

16

12

DTC3

I Dead time control terminal.

17

13

FB3

O Error amplifier output terminal

18

14

− INE3

I Error amplifier inverted input terminal.

19

15

CS3

⎯ Soft-start setting capacitor connection terminal.

31

28

OUT3

O P-ch drive output terminal.

23

20

DTC4

I Dead time control terminal.

22

19

FB4

O Error amplifier output terminal.

21

18

− INE4

I Error amplifier inverted input terminal.

20

17

CS4

⎯ Soft-start setting capacitor connection terminal.

30

27

OUT4

O N-ch drive output terminal.

24

21

DTC5

I Dead time control terminal.

25

22

FB5

O Error amplifier output terminal.

26

23

− INE5

I Error amplifier inverted input terminal.

27

24

CS5

⎯ Soft-start setting capacitor connection terminal.

29

26

OUT5

O N-ch drive output terminal.

13

9

CT

⎯

Triangular wave frequency setting capacitor connection

terminal.

12

8

RT

⎯ Triangular wave frequency setting resistor connection terminal.

(Continued)

4

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