8SLVP2102ANLGI 查看數據表（PDF） - Integrated Device Technology
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8SLVP2102ANLGI
Integrated Device Technology
8SLVP2102ANLGI Datasheet PDF : 23 Pages
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IDT8SLVP2102I Data Sheet
LOW PHASE NOISE, DUAL 1-TO-2, 3.3V, 2.5V LVPECL OUTPUT FANOUT BUFFER
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
PCLKA,
fREF
Input
nPCLKA;
Frequency PCLKB,
nPCLKB
PCLKA,
V/t
Input
nPCLKA;
Edge Rate PCLKB,
1.5
nPCLKB
tPD
Propagation Delay;
NOTE 1
PCLKA, nPCLKA to any
QAx, nQAx or PCLKB, nPCLKB to any
QBx, nQBx for VPP = 0.1V or 0.3V
40
135
tsk(o)
Output Skew; NOTE 2, 3
5
tsk(b)
Bank Skew; NOTE 3, 4
3
tsk(p)
Pulse Skew
fREF = 100MHz
10
tsk(pp)
Part-to-Part Skew;
NOTE 3, 5
100
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
tJIT, SP
Spurious Suppression,
Coupling from QA0 to
QB0
VCMR(PCLKB) = 1V and
fQA0 = 62.5MHz, VPP(PCLKA) = 1V,
VCMR(PCLKA) = 1V
fQB0 = 500MHz, VPP(PCLKB) = 0.15V,
-58
VCMR(PCLKB) = 1V and
fQA0 = 15.625MHz, VPP(PCLKA) = 1V,
-70
VCMR(PCLKA) = 1V
Channel_ISOL Channel Isolation
fREF = 122.88MHz
65
tR / tF
Output Rise/ Fall Time
20% to 80%
25
90
VPP
Peak-to-Peak Input
Voltage; NOTE 6, 8
fREF < 1.5GHz
fREF > 1.5GHz
0.1
0.2
VCMR
Common Mode Input
Voltage; NOTE 6, 7, 8
1.0
VO(pp)
VDIFF_OUT
Output Voltage Swing,
Peak-to-Peak
Differential Output
Voltage Swing,
Peak-to-Peak
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
VCC = 3.3V, fREF 2GHz
VCC = 2.5V, fREF 2GHz
0.40
0.60
0.35
0.55
0.80
1.2
0.70
1.1
Maximum
2
225
15
10
25
175
140
1.5
1.5
VCC – 0.6
1.0
1.0
20
2.0
Units
GHz
V/ns
ps
ps
ps
ps
ps
dB
dB
dB
ps
V
V
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank with equal load conditions. Measured at the differential crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: VIL should not be less than -0.3V. VIH should not be higher than VCC.
NOTE 7: Common mode input voltage is defined at the crosspoint.
NOTE 8: For single-ended LVCMOS input applications, please refer to the Applications Information, Wiring the Differential Input to accept
single-ended levels, Figures 1A and 1B.
IDT8SLVP2102ANLGI REVISION B FEBRUARY 26, 2014
5
©2014 Integrated Device Technology, Inc.
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