W986416CH 查看數據表（PDF） - Winbond
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W986416CH Datasheet PDF : 42 Pages
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W986416CH
1M x 16 bit x 4 Banks SDRAM
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc=3.3V±0.3V, Ta=0° to 70°C Notes:5, 6, 7, 8)
SYMBOL
tRC
tRAS
tRCD
tCCD
tRP
tRRD
tWR
tCK
tCH
tCL
tAC
tOH
tHZ
tLZ
tSB
tT
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
PARAMETER
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b)Command
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CL*=2
CL*=3
CLK Cycle Time
CL*=2
CL*=3
CLK High Level width
CLK Low Level width
Access Time from CLK
CL*=2
CL*=3
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
-6
MIN MAX
60
42 10000
18
1
18
12
10
6
10 1000
6
1000
2.5
2.5
6
5
2
2
6
0
0
6
0.3
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
12
-7
MIN MAX
63
42 10000
20
1
20
14
10
7
10 1000
7
1000
2.5
2.5
6
5.4
2.5
2.5
7
0
0
7
0.3
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
14
-75(PC133)
MIN MAX
65
45 10000
20
1
20
15
10
7.5
10 1000
7.5 1000
2.5
2.5
6
5.4
2.7
2.7
7.5
0
0
7.5
0.3
10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
15
-8H(PC100)
MIN MAX
68
48 10000
20
1
20
20
10
8
10 1000
8
1000
3
3
6
6
3
3
8
0
0
8
0.5
10
2
1
2
1
2
1
2
1
64
16
UNIT
Ns
Cycle
ns
ms
ns
* CL=CAS Latency
Revision 1.2
Publication Release Date: June, 1999
-6-
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