TIMING DIAGRAMS
TIMING DIAGRAMS
IN1,
IN2,
PSAVE
OUTA,
OUTB
tPLH
50%
90%
10%
tPHL
Figure 5. tPLH, tPHL, and tPZH Timing
VDD
t VGON
11 V
VCRES
VDDDETon
2.5 V
VDD
0.8 V
50%
t VDDDET
VDDDEToff
t VDDDET
90%
IM
0%
(<1.0 µA)
Figure 6. Low-Voltage Detection Timing
Figure 7. Charge Pump Timing
Table 6. Truth Table
INPUT
OUTPUT
PSAVE
IN1A
IN2A
IN1B
IN2B
OUT1A
OUT2A
OUT1B
OUT2B
L
L
L
L
L
L
H
L
H
L
L
L
H
L
H
L
H
H
Z
Z
H
X
X
Z
Z
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
PSAVE terminal is pulled up to VDD with internal resistance.
Charge Pump and Low
Voltage Detector
RUN
RUN
RUN
RUN
STOP
Analog Integrated Circuit Device Data
Freescale Semiconductor
17531A
9