MT46V16M8TG-8 查看數據表（PDF） - Micron Technology
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MT46V16M8TG-8 Datasheet PDF : 68 Pages
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Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a
block of columns equal to the burst length is effectively
selected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-Ai when the burst length is set to two, by
A2-Ai when the burst length is set to four and by A3-Ai
when the burst length is set to eight (where Ai is the
most significant column address bit for a given con-
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
figuration). The remaining (least significant) address
bit(s) is (are) used to select the starting location within
the block. The programmed burst length applies to
both READ and WRITE bursts.
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the
starting column address, as shown in Table 1.
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode Register (Mx)
0* 0* Operating Mode CAS Latency BT Burst Length
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
M2 M1 M0
0 00
0 01
0 10
0 11
1 00
1 01
1 10
1 11
Burst Length
M3 = 0
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3 = 1
Reserved
2
4
8
Reserved
Reserved
Reserved
Reserved
M3
Burst Type
0
Sequential
1
Interleaved
M6 M5 M4
000
001
010
011
100
101
110
111
CAS Latency
Reserved
Reserved
2
Reserved
Reserved
Reserved
2.5
Reserved
M11 M10 M9 M8 M7 M6-M0 Operating Mode
0 0 0 0 0 Valid Normal Operation
0 0 0 1 0 Valid Normal Operation/Reset DLL
- - - - - - All other states reserved
Figure 1
Mode Register Definition
TABLE 1
BURST DEFINITION
Burst
Length
2
4
8
Starting Column
Address
A0
0
1
A1 A0
00
01
10
11
A2 A1 A0
000
001
010
011
100
101
110
111
Order of Accesses Within a Burst
Type=Sequential Type=Interleaved
0-1
0-1
1-0
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
NOTE:
1. For a burst length of two, A1-Ai select the two-
data-element block; A0 selects the first access
within the block.
2. For a burst length of four, A2-Ai select the four-
data-element block; A0-A1 select the first access
within the block.
3. For a burst length of eight, A3-Ai select the eight-
data-element block; A0-A2 select the first access
within the block.
4. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
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