DS1340 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS1340 Datasheet PDF : 13 Pages
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I2C RTC with Trickle Charger
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
GND
X1
OSCILLATOR
X2
"C" VERSION ONLY
VCC
VBACKUP
POWER
CONTROL
SCL SERIAL BUS
SDA
INTERFACE
AND ADDRESS
REGISTER
32,768Hz
512Hz
FT/OUT
MUX/BUFFER
DIVIDER AND
CALIBRATION
CIRCUIT
CONTROL
LOGIC
1Hz CLOCK AND
CALENDAR
REGISTERS
DS1340
USER BUFFER
(7 BYTES)
Figure 4. Layout Example
Figure 5. Functional Diagram
error is added by crystal frequency drift caused by
temperature shifts. External circuit noise coupled into
the oscillator circuit can result in the clock running fast.
Figure 4 shows a typical PC board layout for isolating
the crystal and oscillator from noise. Refer to
Application Note 58: Crystal Considerations with Dallas
Real-Time Clocks (www.maxim-ic.com/RTCapps) for
detailed information.
DS1340C Only
The DS1340C integrates a standard 32,768Hz crystal
into the package. Typical accuracy with nominal VCC
and +25°C is approximately +15ppm. Refer to
Application Note 58 for information about crystal accu-
racy vs. temperature.
Operation
The DS1340 operates as a slave device on the serial
bus. Access is obtained by implementing a START
condition and providing a device identification code fol-
lowed by data. Subsequent registers can be accessed
sequentially until a STOP condition is executed. The
device is fully accessible and data can be written and
read when VCC is greater than VPF. However, when
VCC falls below VPF, the internal clock registers are
blocked from any access. If VPF is less than VBACKUP,
the device power is switched from VCC to VBACKUP
when VCC drops below VPF. If VPF is greater than
VBACKUP, the device power is switched from VCC to
VBACKUP when VCC drops below VBACKUP. The regis-
ters are maintained from the VBACKUP source until VCC
is returned to nominal levels. The functional diagram
(Figure 5) shows the main elements of the serial RTC.
Address Map
Table 2 shows the DS1340 address map. The RTC reg-
isters are located in address locations 00h to 06h, and
the control register is located at 07h. The trickle-charge
Table 2. Address Map
ADDRESS
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
BIT 7
EOSC
X
CEB
X
X
X
OUT
TCS3
OSF
BIT 6 BIT 5 BIT 4
10 Seconds
10 Minutes
CB
10 Hours
X
X
X
X
10 Date
X
X
10 Month
10 Year
FT
S
CAL4
TCS2 TCS1 TCS0
0
0
0
BIT 3
X
CAL3
DS1
0
BIT 2
BIT 1
Seconds
Minutes
Hours
Day
Date
Month
Year
CAL2
CAL1
DS0
ROUT1
0
0
BIT 0
CAL0
ROUT0
0
FUNCTION
Seconds
Minutes
Century/Hours
Day
Date
Month
Year
Control
Trickle Charger
Flag
X = Read/Write bit
Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.
RANGE
00–59
00–59
0–1; 00–23
01–07
01–31
01–12
00–99
—
—
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