24C64 查看數據表（PDF） - Microchip Technology

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24C64

64K SPI™ Bus Serial EEPROM

Microchip Technology 

25AA640/25LC640/25C640

3.7 Data Protection

3.8 Power On State

The following protection has been implemented to pre-

vent inadvertent writes to the array:

• The write enable latch is reset on power-up.

• A write enable instruction must be issued to set

the write enable latch.

• After a byte write, page write, or status register

write, the write enable latch is reset.

• CS must be set high after the proper number of

clock cycles to start an internal write cycle.

• Access to the array during an internal write cycle

is ignored and programming is continued.

The 25xx640 powers on in the following state:

• The device is in low power standby mode (CS = 1).

• The write enable latch is reset.

• SO is in high impedance state.

• A high to low transition on CS is required to enter

the active state.

.

TABLE 3-3:

WPEN

X

0

1

X

WRITE PROTECT FUNCTIONALITY MATRIX

WP

WEL

Protected Blocks

Unprotected Blocks

X

0

X

1

Low

1

High

1

Protected

Protected

Protected

Protected

Protected

Writable

Writable

Writable

Status Register

Protected

Writable

Protected

Writable

DS21223A-page 10

Preliminary

© 1997 Microchip Technology Inc.

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