24LC09T 查看數據表（PDF） - Microchip Technology
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24LC09T Datasheet PDF : 18 Pages
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24LC09
1.2 AC Characteristics
AC Characteristics
Industrial (I):
TAMB = -40°C to +85°C
Param.
No.
Sym
Parameter
Min
Max Units
Conditions
1
FCLK Clock frequency
—
400 kHz
—
100
2
THIGH Clock high time
600
—
ns
3
TLOW Clock low time
1300
—
ns
4
TR SDA and SCL rise time
—
300 ns
5
TF SDA and SCL fall time
—
300 ns
6 THD:STA START condition hold time
600
—
ns
7 TSU:STA START condition setup time
600
—
ns
8 THD:DAT Data input hold time
0
—
ns
9 TSU:DAT Data input setup time
100
—
ns
10 TSU:STO STOP condition setup time
600
—
ns
11
TAA Output valid from clock
(Note 2)
—
900 ns
12
TBUF Bus free time: Time the bus
must be free before a new
transmission can start
1300
—
ns
13
TOF Output fall time from VIH
minimum to VIL maximum
20+0.1CB 250 ns
14
TSP Input filter spike suppression
(SDA and SCL pins)
—
50 ns
15
TWC Write cycle time (byte or page)
—
5
ms
16
Endurance
1M
— cycles
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
4.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (Note 1)
(Note 1)
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
(Note 2)
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V
2.5V ≤ VCC ≤ 5.5V (Note 1)
(Notes 1 and 3)
25°C, VCC = 5.0V, Block Mode
(Note 4)
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on Microchip’s website.
2004 Microchip Technology Inc.
DS21675B-page 3
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