24AA52T-IP 查看數據表（PDF） - Microchip Technology
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24AA52T-IP Datasheet PDF : 36 Pages
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24AA52/24LCS52
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
Symbol PDIP
SOIC TSSOP MSOP DFN(1) TDFN(1)
Description
A0
A1
A2
VSS
SDA
SCL
WP
VCC
Note 1:
1
1
1
1
1
1 Chip Address Input
2
2
2
2
2
2 Chip Address Input
3
3
3
3
3
3 Chip Address Input
4
4
4
4
4
4 Ground
5
5
5
5
5
5 Serial Address/Data I/O
6
6
6
6
6
6 Serial Clock
7
7
7
7
7
7 Write-Protect Input
8
8
8
8
8
8 +1.8V to 5.5V Power Supply
The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
2.1 A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24XXX52 devices may be connected to the
same bus by using different Chip Select bit
combinations. These inputs must be connected to
either VSS or VCC.
2.2 Serial Address/Data Input/Output
(SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pull-
up resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4 Write-Protect (WP)
This is the hardware write-protect pin. It can be tied to
VCC or VSS. If tied to VCC, the hardware write protection
is enabled. If the WP pin is tied to VSS, the hardware
write protection is disabled.
1996-2011 Microchip Technology Inc.
DS21166K-page 5
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