25AA640A 查看數據表（PDF） - Microchip Technology

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25AA640A

64K SPI Bus Serial EEPROM

Microchip Technology 

BLOCK DIAGRAM

STATUS

Register

25AA640A/25LC640A

HV Generator

I/O Control

Logic

Memory X

Control

Logic Dec

EEPROM

Array

Page Latches

SI

SO

CS

SCK

HOLD

WP

VCC

VSS

Y Decoder

Sense Amp.

R/W Control

TABLE 2-1: INSTRUCTION SET

Instruction Name Instruction Format

READ

0000 0011

WRITE

0000 0010

WRDI

0000 0100

WREN

0000 0110

RDSR

0000 0101

WRSR

0000 0001

Description

Read data from memory array beginning at selected address

Write data to memory array beginning at selected address

Reset the write enable latch (disable write operations)

Set the write enable latch (enable write operations)

Read STATUS register

Write STATUS register

FIGURE 2-1: READ SEQUENCE

CS

SCK

SI

SO

0 1 2 3 4 5 6 7 8 9 10 11

21 22 23 24 25 26 27 28 29 30 31

Instruction

16-bit Address

0 0 0 0 0 0 1 1 15 14 13 12

210

High-Impedance

Data Out

76543210

 2003-2013 Microchip Technology Inc.

DS21830F-page 7

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