24C320-P 查看數據表（PDF） - Microchip Technology

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24C320-P

32K SPI™ Bus Serial EEPROM

Microchip Technology 

25AA320/25LC320/25C320

3.6 Write Status Register Instruction

(WRSR)

The Write Status Register instruction (WRSR) allows the

user to select one of four levels of protection for the

array by writing to the appropriate bits in the Status

register. The array is divided up into four segments.

The user has the ability to write-protect none, one, two,

or all four of the segments of the array. The partitioning

is controlled as shown in Table 3-2.

The Write-Protect Enable (WPEN) bit is a nonvolatile

bit that is available as an enable bit for the WP pin. The

Write-Protect (WP) pin and the Write-Protect Enable

(WPEN) bit in the Status register control the program-

mable hardware write-protect feature. Hardware write

protection is enabled when WP pin is low and the

WPEN bit is high. Hardware write protection is disabled

when either the WP pin is high or the WPEN bit is low.

When the chip is hardware write-protected, only writes

to nonvolatile bits in the Status register are disabled.

See Table 3-3 for a matrix of functionality on the WPEN

bit.

See Figure 3-7 for the WRSR timing sequence.

TABLE 3-2: ARRAY PROTECTION

BP1

BP0

Array Addresses

Write-Protected

0

0

none

0

1

upper 1/4

(0C00h - 0FFFh)

1

0

upper 1/2

(0800h - 0FFFh)

1

1

all

(0000h - 0FFFh)

FIGURE 3-7: WRITE STATUS REGISTER TIMING SEQUENCE

CS

SCK

SI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

instruction

data to Status register

0 00 00 0 01 7 6 54 3 2 10

High-impedance

SO

 2004 Microchip Technology Inc.

DS21227E-page 11

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