AS6UA5128-BI(2000) 查看數據表（PDF） - Alliance Semiconductor

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AS6UA5128-BI
(Rev.:2000)

2.3V to 3.6V 512K×8 Intelliwatt low-power CMOS SRAM

Alliance Semiconductor 

AS6UA5128

®

Read cycle (over the operating range)3,9

–55

Parameter

Symbol Min Max

Read cycle time

tRC

55

–

Address access time

tAA

–

55

Chip select (CS) access time

tACS

–

55

Output enable (OE) access time

tOE

–

25

Output hold from address change tOH

10

–

CS low to output in low Z

tCLZ

10

–

CS high to output in high Z

tCHZ

0

20

OE low to output in low Z

tOLZ

5

–

OE high to output in high Z

tOHZ

0

20

Power up time

tPU

0

–

Power down time

tPD

–

55

–70

Min Max Unit

70

–

ns

–

70

ns

–

70

ns

–

35

ns

10

–

ns

10

–

ns

0

20

ns

5

–

ns

0

20

ns

0

–

ns

–S

70

ns

Notes

3

3

5

4, 5

4, 5

4, 5

4, 5

4, 5

S

Key to switching waveforms

Rising input

Falling input

Read waveform 1 (address controlled)3,6,7,9

tRC

Address

tOH

tAA

DOUT

Previous data valid

Data valid

Undefined/don’t care

tOH

Read waveform 2 (CS, OE controlled)3,6,8,9

tRC1

CS

tOE

OE

DOUT

tACE

tOLZ

Data valid

tOHZ

tCHZ

Supply

current

tCLZ

tPU

50%

tPD

ICC

50%

ISB

4

ALLIANCE SEMICONDUCTOR

10/6/00

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