HFA3683A 查看數據表（PDF） - Intersil

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HFA3683A

2.4GHz RF/IF Converter and Synthesizer

Intersil 

HFA3683A

REF_IN

R COUNTER

R

TO

DC OFFSET

CAL

V

ISOURCE

N COUNTER

RESET

A

DUAL MODULUS

CONTROL

P/P+1

B

PRESCALER

RESET

LO_IN+

ISINK

CP_D0

VCONTROL

VCO

FIGURE 1. PLL SIMPLIFIED BLOCK DIAGRAM

DATA BIT 20: MSB

BIT 19

BIT 10 BIT 9

BIT 1

CLOCK

LE

tCS

tCH

OR

LE

tCWL

tCWH

tES

NOTES:

9. Parenthesis data indicates programmable reference divider data.

10. Data shifted into register on clock rising edge.

11. Data is shifted in MSB first.

FIGURE 2. SERIAL DATA INPUT TIMING

BIT 1: LSB

tEW

2-8

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