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HFA3624 查看數據表(PDF) - Intersil

零件编号
产品描述 (功能)
生产厂家
HFA3624
Intersil
Intersil Intersil
HFA3624 Datasheet PDF : 19 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
HFA3624
Electrical Specifications VCC = +2.7V, LO = 2170MHz, IF = 280MHz, RF = 2450MHz, ZO = 50,
Unless Otherwise Specified (Continued)
PARAMETER
SYMBOL
TEMP (oC)
MIN
TYP
MAX
UNITS
TRANSMIT MIXER/POWER PRE-AMP CASCADED CHARACTERISTICS (TXM_IF+ = 280MHz/-13dBm, -3dB Loss RF Image Filter with no LO
suppression between Mixer and Transmit Amp, RL = 50, RSIF =
250(Note 6))
Cascaded Power Gain
CTX_PG
25
8
11.4
-
dB
85
5.5
-
-
dB
Cascaded Output P1dB
CTX_P1D
25
-
-2.0
-
dBm
Cascaded Output NF
CTX_NF
25
-
15
-
dB
Cascaded Output 3rd Order Intercept
CTX_IP3
25
-
7.1
-
dBm
Cascaded LO Leakage
CTX_LEAK
25
-
-8.7
-
dBm
POWER SUPPLY AND LOGIC CHARACTERISTICS
Voltage Supply Range
Transmit Mode Supply Current (VCC = 2.7V)
VCC
25
TX_2.7ICC
25
85
2.7
-
5.5
V
32
49
57
mA
43
-
64
mA
Receive Mode Supply Current (VCC = 2.7V)
RX_ICC
25
10
18
20.5
mA
85
19
22.5
24
mA
Power Down Current (VCC = 5.5V)
Logic Input Low Level
Logic Input High Level
Logic Low Input Bias Current (VPE = 0V, VCC = 5.5V)
Logic High Input Bias Current (VPE = 5.5V, VCC = 5.5V)
TX/RX Power Enable Time (Note 7)
ICC_PD
VIL
VIH
IB_LO
IB_HI
PEt
Full
-
0.3
10
µA
Full
-0.2
-
0.8
V
Full
2.0
-
VCC
V
Full
-
-
1
µA
Full
-
-
150
µA
Full
-
0.25
1
µs
TX/RX Power Disable Time (Note 7)
PDt
Full
-
0.25
1
µs
NOTES:
2. See Figure 5 Test Circuit for 50IF matching network component values.
3. SSB (Single Side Band) Noise Figure measurement requires the use of an IF Reject/Highpass Filter between the Noise Source and the RXM_RF
port. This filter prevents IF input noise from interfering with the Mixer IF output Noise Figure Measurement.
4. Transmit mixer measured with Impedance Transform Network 250at device to 50at the source. Refer to Figure 5, pin 19.
5. Implied limit, production measurement uses 50termination at pin 19 (RSIF = 50). Typical transmit conversion gain increase of 5.5dB with
application circuit Figure 5 (RSIF = 250).
6. See Figure 2 for Typical Application Circuit.
7. Enable/Disable Time Specifications are tested with the external component values shown in the Figure 5 Test Circuit, with an IF frequency of
280MHz. Specifically the AC coupling capacitors on the TXM_IF+ and TXM_IF- pins are biased up to operating voltage from a fixed internal
current source at power up. Increasing these AC coupling capacitors above 1000pF will slow Enable Time proportionately.
POWER CONTROL TRUTH TABLE
STATE
RX_PE
Power Down
Low
(Receive/Transmit Channels Power Down)
Transmit Mode
Low
(Receive Channel Power Down)
Receive Mode
(Transmit Channel Power Down)
High
Not Recommended
High
TX_PE
Low
High
Low
High
2-31

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