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CA16A2FNN

CA16-Type 2.5 Gbits/s DWDM Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

CA16-Type 2.5 Gbits/s DWDM Transponder with

16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Advance Data Sheet

March 2001

Pin Descriptions (continued)

Table 2. CA16-Type Transponder Input Pin Descriptions

Pin Name

Pin Description

TxD[0:15]P

TxD[0:15]N

PICLKP

PICLKN

TxREFCLKP

TxREFCLKN

TxDIS

WS

DLOOP

LLOOP

PHINIT

FRAMEN*

OOF*

RESET

16-Bit Differential LVPECL Parallel Input Data Bus. TxD15P/N is the most significant bit of the

input word and is the first bit serialized. TxD00P/N is the least significant bit of the input word and

is the last bit serialized. TxD[0:15]P/N is sampled on the rising edge of PICLK.

Differential LVPECL Parallel Input Clock. A 155 MHz nominally 50% duty cycle input clock to

which TxD[0:15]P/N is aligned. The rising edge of PICLK transfers the data on the 16 TxD inputs

into the holding register of the parallel-to-serial converter.

Differential LVPECL Low Jitter 155.520 MHz Input Reference Clock. This input is used as the

reference for the internal clock frequency synthesizer, which generates the 2.5 GHz bit rate clock

used to shift data out of the parallel-to-serial converter and also for the byte-rate clock, which

transfers the 16-bit parallel input data from the input holding register into the parallel-to-serial shift

register. Input is internally terminated and biased. See discussion on timing interface, page 18.

Transmitter Disable Input. A logic high on this input pin shuts off the transmitter’s laser so that

there is no optical output.

Wavelength Select. When this input is a logic 0 or left floating, the output wavelength will be the

nominal wavelength (at 25 °C); when it is a logic 1, the wavelength will increase by approximately

0.8 nm (100 GHz frequency decrease).

Diagnostic Loopback Enable (LVTTL). When the DLOOP input is low, the 2.5 Gbits/s serial data

stream from the parallel-to-serial converter is looped back internally to the serial-to-parallel con-

verter along with an internally generated bit synchronous serial clock. The received serial data

path from the optical receiver is disabled.

Line Loopback Enable (LVTTL). When LLOOP is low, the 2.5 Gbits/s serial data and recovered

clock from the optical receiver are looped directly back to the optical transmitter. The multiplexed

serial data from the parallel-to-serial converter is ignored.

Phase Initialization (Single-Ended LVPECL). This input is used to align the internal elastic store

(FIFO). A rising edge on PHINIT will realign the internal timing (see FIFO discussion, pages 12

and 18).

Frame Enable Input (LVTTL). Enables the frame detection circuitry to detect A1, A2 byte align-

ment and to lock to a word boundary. The CA16 transponder will continually perform frame acqui-

sition as long as FRAMEN is held high. When this input is low, the frame-detection circuitry is

disabled. Frame-detection process is initiated by rising edge of out-of-frame pulse.

Out of Frame (LVTTL). This input indicator is typically generated by external SONET/SDH over-

head monitor circuitry in response to a state in which the frame boundaries of the received

SONET/SDH signal are unknown, i.e., after system reset or loss of synchronization. The rising

edge of the OOF input initiates the frame detection function if FRAMEN is high. The FP output

goes high when the frame boundary is detected in the incoming serial data stream from the opti-

cal receiver.

Master Reset (LVTTL). Reset input for the multiplexer and demultiplexer. A logic low on this input

clears all buffers and registers. During RESET, POCLK and PCLK do not toggle.

* Future versions of the cooled transponder will not support the frame-detect function.

10

Agere Systems Inc.

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