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CA16A2CNN 查看數據表(PDF) - Agere -> LSI Corporation

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CA16A2CNN Datasheet PDF : 30 Pages
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CA16-Type 2.5 Gbits/s DWDM Transponder with
16-Channel 155 Mbits/s Multiplexer/Demultiplexer
Advance Data Sheet
March 2001
Pin Descriptions
Table 1. CA16-Type Transponder Pinout
Pin # Pin Name I/O
Logic
Description
01
FGND
I
Supply Frame Ground1
02
IPDMON
O
Analog Receiver Photodiode Current Monitor
03
TxDGND
I
Supply Transmitter Digital Ground
04
TxD15P
I
LVPECL Transmitter 155 Mbits/s MSB Data Input
05
TxD15N
I
LVPECL Transmitter 155 Mbits/s MSB Data Input
06
TxD13P
I
LVPECL Transmitter 155 Mbits/s Data Input
07
TxD13N
I
LVPECL Transmitter 155 Mbits/s Data Input
08
TxDGND
I
Supply Transmitter Digital Ground
09
TxD11P
I
LVPECL Transmitter 155 Mbits/s Data Input
10
TxD11N
I
LVPECL Transmitter 155 Mbits/s Data Input
11
TxD09P
I
LVPECL Transmitter 155 Mbits/s Data Input
12
TxD09N
I
LVPECL Transmitter 155 Mbits/s Data Input
13
TxDGND
I
SUPPLY Transmitter Digital Ground
14
TxD07P
I
LVPECL Transmitter 155 Mbits/s Data Input
15
TxD07N
I
LVPECL Transmitter 155 Mbits/s Data Input
16
TxD05P
I
LVPECL Transmitter 155 Mbits/s Data Input
17
TxD05N
I
LVPECL Transmitter 155 Mbits/s Data Input
18
TxDGND
I
Supply Transmitter Digital Ground
19
TxD03P
I
LVPECL Transmitter 155 Mbits/s Data Input
20
TxD03N
I
LVPECL Transmitter 155 Mbits/s Data Input
21
TxD01P
I
LVPECL Transmitter 155 Mbits/s Data Input
22
TxD01N
I
LVPECL Transmitter 155 Mbits/s Data Input
23
TxDGND
I
Supply Transmitter Digital Ground
24
PICLKP
I
LVPECL Byte-Aligned Parallel Input Clock at 155 MHz
25
PICLKN
I
LVPECL Byte-Aligned Parallel Input Clock at 155 MHz
26
LOCKDET
O
LVTTL Lock Detect
27
TxDGND
I
Supply Transmitter Digital Ground
28
Tx3.3D
I
Supply Transmitter 3.3 V Digital Supply
29
Tx3.3D
I
Supply Transmitter 3.3 V Digital Supply
30
TxAGND
I
Supply Transmitter Analog Ground
31
Tx3.3A
I
Supply Transmitter 3.3 V Analog Supply
32
Tx3.3A
I
Supply Transmitter 3.3 V Analog Supply
33
TxAGND
I
Supply Transmitter Analog Ground
34
LPM
O
Analog Laser Power Monitor
35
LSRALM
O 5 V CMOS Laser Degrade Alarm
36
LSRBIAS
O
Analog Not Implemented on the CA16-TypeTransponder
37
NC
No User Connection Permitted2
38
DLOOP
I
LVTTL Diagnostic Loopback
39
WDEA
O 5 V CMOS Wavelength Deviation Error Alarm
40
FP
O LVPECL Frame Pulse
41
FRAMEN
I
LVTTL Frame Enable
1. Frame ground is connected to the housing and is isolated from all circuit grounds (TxDGND, TxAGND, RxDGND, RxAGND).
2. Pins labeled no connection must remain open circuits; they have internal voltages and must not be connected to VCC, Ground,
or any signal node.
6
Agere Systems Inc.

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