TA16L1FAA 查看數據表（PDF） - Agere -> LSI Corporation

零件编号

产品描述 (功能)

生产厂家

TA16L1FAA

TA16-Type 2.5 Gbits/s Transponder with 16-Channel 155 Mbits/s Multiplexer/Demultiplexer

Agere -> LSI Corporation 

TA16-Type 2.5 Gbits/s Transponder with

16-Channel 155 Mbits/s Multiplexer/Demulitplexer

Data Sheet

March 2001

Pin Descriptions (continued)

Table 2. TA16-Type Transponder Input Pin Descriptions

Pin Name

Pin Description

TxD[0:15]P

TxD[0:15]N

PICLKP

PICLKN

TxREFCLKP

TxREFCLKN

TxDIS

DLOOP

LLOOP

PHINIT

FRAMEN

OOF

RESET

16-bit Differential LVPECL Parallel Input Data Bus. TxD15P/N is the most signifi-

cant bit of the input word and is the first bit serialized. TxD00P/N is the least signifi-

cant bit of the input word and is the last bit serialized. TxD[0:15]P/N is sampled on

the rising edge of PICLK.

Differential LVPECL Parallel Input Clock. A 155 MHz nominally 50% duty cycle

input clock to which TxD[0:15]P/N is aligned. The rising edge of PICLK transfers the

data on the 16 TxD inputs into the holding register of the parallel-to-serial converter.

Differential LVPECL Low Jitter 155.520 MHz Input Reference Clock. This input is

used as the reference for the internal clock frequency synthesizer which generates

the 2.5 GHz bit rate clock used to shift data out of the parallel-to-serial converter and

also for the byte-rate clock, which transfers the 16-bit parallel input data from the

input holding register into the parallel-to-serial shift register. Input is internally termi-

nated and biased. See discussion on interfacing, page 13.

Transmitter Disable Input. A logic HIGH on this input pin shuts off the transmitter’s

laser so that there is no optical output.

Diagnostic Loopback Enable (LVTTL). When the DLOOP input is low, the

2.5 Gbits/s serial data stream from the parallel-to-serial converter is looped back

internally to the serial-to-parallel converter along with an internally generated bit syn-

chronous serial clock. The received serial data path from the optical receiver is dis-

abled.

Line Loopback Enable (LVTTL). When LLOOP is low, the 2.5 Gbits/s serial data and

recovered clock from the optical receiver are looped directly back to the optical trans-

mitter. The multiplexed serial data from the parallel-to-serial converter is ignored.

Phase Initialization (LVPECL). A rising edge on this input will realign the internal

timing associated with clocking data into and out of the internal FIFO. For a detailed

explanation, see the section on Transmitter Data Input Timing on page 17.

Frame Enable Input (LVTTL). Enables the frame detection circuitry to detect A1

A2 byte alignment and to lock to a word boundary. The TA16 transponder will contin-

ually perform frame acquisition as long as FRAMEN is held high. When this input is

low, the frame-detection circuitry is disabled. Frame-detection process is initiated by

rising edge of out-of-frame pulse.

Out of Frame (LVTTL). This input indicator is typically generated by external

SONET/SDH overhead monitor circuitry in response to a state in which the frame

boundaries of the received SONET/SDH signal are unknown, i.e., after system reset

or loss of synchronization. The rising edge of the OOF input initiates the frame detec-

tion function if FRAMEN is high. The FP output goes high when the frame boundary

is detected in the incoming serial data stream from the optical receiver.

Master Reset (LVTTL). Reset input for the multiplexer/demultiplexer. A low on this

input clears all buffers and registers. During reset, POCLK and PCLK do not toggle.

10

Agere Systems Inc.

Share Link: