AD5313ARU-REEL7(RevA) 查看數據表（PDF） - Analog Devices

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AD5313ARU-REEL7
(Rev.:RevA)

2.5 V to 5.5 V, 230 μ
A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs

Analog Devices 

AD5303/AD5313/AD5323

FUNCTIONAL DESCRIPTION

The AD5303/AD5313/AD5323 are dual resistor-string DACs

fabricated on a CMOS process with resolutions of 8, 10 and 12

bits respectively. They contain reference buffers and output

buffer amplifiers, and are written to via a 3-wire serial interface.

They operate from single supplies of 2.5 V to 5.5 V and the

output buffer amplifiers provide rail-to-rail output swing with a

slew rate of 0.7 V/µs. Each DAC is provided with a separate

reference input, which may be buffered to draw virtually no

current from the reference source, or unbuffered to give a refer-

ence input range from GND to VDD. The devices have three

programmable power-down modes, in which one or both DACs

may be turned off completely with a high impedance output, or

the output may be pulled low by an on-chip resistor.

Digital-to-Analog Section

The architecture of one DAC channel consists of a reference

buffer and a resistor-string DAC followed by an output buffer

amplifier. The voltage at the VREF pin provides the reference

voltage for the DAC. Figure 5 shows a block diagram of the

DAC architecture. Since the input coding to the DAC is straight

binary, the ideal output voltage is given by

where

VOUT

= VREF × D

2N

D = decimal equivalent of the binary code, which is loaded to

the DAC register:

0–255 for AD5303 (8 bits)

0–1023 for AD5313 (10 bits)

0–4095 for AD5323 (12 bits)

N = DAC resolution

VREFA

REFERENCE

BUFFER

BUF A

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

VOUTA

OUTPUT BUFFER

AMPLIFIER

Figure 5. Single DAC Channel Architecture

Resistor String

The resistor string section is shown in Figure 6. It is simply a

string of resistors, each of value R. The digital code loaded to

the DAC register determines at what node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

R

R

R

TO OUTPUT

AMPLIFIER

R

R

Figure 6. Resistor String

DAC Reference Inputs

There is a reference input pin for each of the two DACs. The

reference inputs are buffered but can also be configured as

unbuffered. The advantage with the buffered input is the high

impedance it presents to the voltage source driving it. However,

if the unbuffered mode is used, the user can have a reference

voltage as low as GND and as high as VDD since there is no

restriction due to headroom and footroom of the reference

amplifier.

If there is a buffered reference in the circuit (e.g., REF192),

there is no need to use the on-chip buffers of the AD5303/

AD5313/AD5323. In unbuffered mode, the input impedance is

still large at typically 180 kΩ per reference input for 0 V to

VREF mode and 90 kΩ for 0 V to 2 VREF mode.

The buffered/unbuffered option is controlled by the BUF A and

BUF B pins. If the BUF pin is tied high, the reference input is

buffered, if tied low, it is unbuffered.

Output Amplifier

The output buffer amplifier is capable of generating output

voltages to within 1 mV of either rail, which gives an output

range of 0.001 V to VDD – 0.001 V when the reference is VDD.

It is capable of driving a load of 2 kΩ in parallel with 500 pF to

GND and VDD. The source and sink capabilities of the output

amplifier can be seen in TPC 11.

The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB

(at eight bits) of 6 µs.

POWER-ON RESET

The AD5303/AD5313/AD5323 are provided with a power-on

reset function, so that they power up in a defined state. The

power-on state is

• Normal operation

• 0 V to VREF output range

• Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain

so until a valid write sequence is made to the device. This is

particularly useful in applications where it is important to know

the state of the DAC outputs while the device is powering up.

Clear Function (CLR)

The CLR pin is an active low input that, when pulled low, loads

all zeros to both input registers and both DAC registers. This

enables both analog outputs to be cleared to 0 V.

REV. A

–11–

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