AD5313BRU-REEL(RevA) 查看數據表（PDF） - Analog Devices
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AD5313BRU-REEL
(Rev.:RevA)
(Rev.:RevA)
Analog Devices
AD5313BRU-REEL Datasheet PDF : 20 Pages
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2.5 V to 5.5 V, 230 A, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
AD5303/AD5313/AD5323*
FEATURES
AD5303: 2 Buffered 8-Bit DACs in 1 Package
A Version: ؎1 LSB INL, B Version: ؎0.5 LSB INL
AD5313: 2 Buffered 10-Bit DACs in 1 Package
A Version: ؎4 LSB INL, B Version: ؎2 LSB INL
AD5323: 2 Buffered 12-Bit DACs in 1 Package
A Version: ؎16 LSB INL, B Version: ؎8 LSB INL
16-Lead TSSOP Package
Micropower Operation: 300 A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to VREF or 0 V to 2 VREF
Power-On-Reset to 0 V
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single 2.5 V to 5.5 V supply consuming 230 µA at
3 V. Their on-chip output amplifiers allow the outputs to swing
rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/AD5313/
AD5323 utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with standard SPI®,
QSPI™, MICROWIRE™, and DSP interface standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured as
buffered or unbuffered inputs. The parts incorporate a power-on
reset circuit, which ensures that the DAC outputs power-up to
0 V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The parts
contain a power-down feature that reduces the current consump-
tion of the devices to 200 nA at 5 V (50 nA at 3 V) and provides
software-selectable output loads while in power-down mode. The
parts may also be used in daisy-chaining applications using the
SDO pin.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equipment.
The power consumption is 1.5 mW at 5 V, 0.7 mW at 3 V,
reducing to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VDD
BUF A
VREFA
SYNC
SCLK
DIN
POWER-ON
RESET
INPUT
REGISTER
INTERFACE
LOGIC
>
DAC
REGISTER
AD5303/AD5313/AD5323
STRING
DAC
BUFFER
POWER-DOWN
LOGIC
VOUTA
RESISTOR
NETWORK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
BUFFER
VOUTB
SDO
GAIN-SELECT
LOGIC
RESISTOR
NETWORK
DCEN LDAC CLR
PD
BUF B
VREFB
GND
*Protected by U.S. Patent No. 5684481; other patents pending.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
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Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
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