AD5313BRU-REEL(RevA) 查看數據表（PDF） - Analog Devices

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AD5313BRU-REEL
(Rev.:RevA)

2.5 V to 5.5 V, 230 μ
A, Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs

Analog Devices 

VDD = 3V

VDD = 5V

0

100 150 200 250 300 350 400

IDD (␮A)

TPC 10. IDD Histogram with

VDD = 3 V and VDD = 5 V

600

BOTH DACS IN GAIN-OF-TWO MODE

REFERENCE INPUTS BUFFERED

500

400

–40؇C

+25؇C

300

+105؇C

200

100

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD (V)

TPC 13. Supply Current vs.

Supply Voltage

AD5303/AD5313/AD5323

5

5V SOURCE

4

3

3V SOURCE

2

1

3V SINK

5V SINK

0

0

1

2

3

4

5

6

SINK/SOURCE CURRENT (mA)

TPC 11. Source and Sink

Current Capability

600

500

400

300

200

100

0

ZERO SCALE

VDD = 5V

TA = 25؇C

FULL SCALE

TPC 12. Supply Current vs. Code

1.0

0.9 BOTH DACS IN

THREE-STATE CONDITION

0.8

0.7

0.6

0.5

0.4

+105؇C

0.3

–40؇C

0.2

+25؇C

0.1

0

2.7 3.2 3.7 4.2 4.7 5.2

VDD (V)

TPC 14. Power-Down Current

vs. Supply Voltage

700

TA = 25؇C

600

500

400

VDD = 5V

300

200

VDD = 3V

100

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

VLOGIC (V)

TPC 15. Supply Current vs.

Logic Input Voltage

CH2 CLK

VDD = 5V

TA = 25؇C

TA = 25؇C

VDD

CH1

VOUT

CH1 1V, CH2 5V, TIME BASE = 5␮s/DIV

TPC 16. Half-Scale Settling (1/4 to

3/4 Scale Code Change)

CH1

CH2

VOUTA

CH1 1V, CH2 1V, TIME BASE = 20␮s/DIV

TPC 17. Power-On Reset to 0 V

TA = 25؇C

CH1

CH3 CLK

CH1 1V, CH3 5V, TIME BASE = 1␮s/DIV

TPC 18. Exiting Power-Down

to Midscale

REV. A

–9–

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