V826532K04SXTG-B1 查看數據表（PDF） - Mosel Vitelic Corporation
零件编号
产品描述 (功能)
生产厂家
V826532K04SXTG-B1
Mosel Vitelic Corporation
V826532K04SXTG-B1 Datasheet PDF : 14 Pages
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MOSEL VITELIC
V826532K04S
Serial Presence Detect Information (cont.)
Function Supported
Hex value
Byte #
Function described
A1 B0 B1 A1 B0 B1
29 Minimum RAS to CAS delay(=tRCD)
30 Minimum active to precharge time(=tRAS)
31 Module ROW density
20ns 20ns 18ns 50h 50h 48h
50ns 45ns 45ns 32h 2Dh 2Dh
128MB
20h
32 Command and address signal input setup time
1.1ns 0.9ns 0.9ns B0h 90h 90h
33 Command and address signal input hold time
1.1ns 0.9ns 0.9ns B0h 90h 90h
34 Data signal input setup time
0.6ns 0.5ns 0.5ns 60h 50h 50h
35 Data signal input hold time
0.6ns 0.5ns 0.5ns 60h 50h 50h
36-40 Superset information (may be used in future)
00h
41 SDRAM device minimum active to active/auto-refresh time
(=tRC)
70ns 65ns 60ns 46h 41h 3Ch
42 SDRAM device minimum active to autorefresh to active/auto-refresh 80ns 75ns 67ns 50h 4Bh 43h
time (=tRFC)
43 SDRAM device maximum device cycle time (=tCK MAX)
12ns 12ns 12ns 30h 30h 30h
44 SDRAM device maximum skew between DQS and DQ signals
(=tDQSQ)
0.6ns 0.5ns 0.5ns 3Ch 32h 32h
45 SDRAM device maximum read datahold skew factor (=tQHS)
1ns 0.75ns 0.75ns A0h 75h 75h
46-61 Superset information (may be used in future)
-
00h
62 SPD data revision code
Initial release
00h
63 Checksum for Bytes 0 ~ 62
-
C5h 0Bh AAh
64 Manufacturer JEDEC ID code
Mosel Vitelic
40h
65 -71 ....... Manufacturer JEDEC ID code
Mosel Vitelic
40h
72 Manufacturing location
01h
73-90 Module part number (ASCII)
V826532K04S
91 Manufacturer revison code (For PCB)
0
00
92 Manufacturer revison code (For component)
0
00
93 Manufacturing date (Week)
-
-
94 Manufacturing date (Year)
-
-
95~98 Assembly serial #
-
-
99~127 Manufacturer specific data (may be used in future)
Undefined
00h
128~255 Open for customer use
Undefined
00h
V826532K04S Rev. 1.2 March 2002
6
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