V826532K04SXTG-B1 查看數據表（PDF） - Mosel Vitelic Corporation
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V826532K04SXTG-B1
Mosel Vitelic Corporation
V826532K04SXTG-B1 Datasheet PDF : 14 Pages
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MOSEL VITELIC
V826532K04S
DDR SDRAM MODULE IDD SPEC TABLE
Symbol
B1
(DDR266@CL=2)
Typical
Worst
IDD0
1210
1230
IDD1
1440
1530
IDD2P
610
650
IDD2F
770
850
IDD2Q
690
730
IDD3P
650
690
IDD3N
810
890
IDD4R
1770
2000
IDD4W
1890
2200
IDD5
1890
2200
IDD6
Normal
32
32
Low power
16
16
IDD7
3100
3500
B0
(DDR266@ CL=2.5)
Typical
Worst
1210
1230
1440
1530
610
650
770
850
690
730
650
690
810
890
1770
2000
1890
2200
1890
2200
32
32
16
16
3100
3500
A1
(DDR200@CL=2)
Typical Worst
980
1050
1130
1250
490
530
650
690
570
600
530
570
650
730
1450
1650
1530
1690
1530
1690
32
32
16
16
2450
2850
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Detailed test conditions for DDR SDRAM IDD1 & IDD
IDD1 : Operating current: One bank operation
1. Typical Case : Vdd = 2.5V, T=25’ C
2. Worst Case : Vdd = 2.7V, T= 10’ C
3. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
4. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
V826532K04S Rev. 1.2 March 2002
9
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