HFA3664 查看數據表（PDF） - Intersil

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HFA3664

2.7GHz UpConverter with Gain Control

Intersil 

HFA3664

Electrical Specifications VCC = 5.5V, LO = 2400MHz, IF = 100MHz, RF = 2500MHz, ZO = 50W,

Unless Otherwise Specified (Continued)

PARAMETER

(NOTE 2)

SYMBOL

TEST

TEMP

LEVEL

(oC)

MIN

TYP

MAX UNITS

TRANSMIT POWER PREAMP CHARACTERISTICS (PRE_IN = 2400MHz/-30dBm, AGC_CTRL = 0.7V (Max Gain))

Frequency Range

PRE_f

B

25

2.3

-

2.7

GHz

Power Gain

(AGC_CTRL = 0.7V)

VCC = 5.5V

PRE_PGH

A

25, 85

21

24

27

dB

Pre-Amp Noise Figure (Max Gain)

PRE_NF

B

25

-

8

-

dB

Pre-Amp AGC Range (Max - Min Gain)

PRE_AGC

A

25, 85

20

30

-

dB

AGC Control Voltage Range

AGC_V

A

25, 85

0.7

-

1.7

V

AGC Control Linearity

AGC_LIN

B

25

-

5:1

-

-

AGC Settling Time (Min to Max Gain)

AGC_T1

B

25

-

8.0

-

µS

AGC Settling Time (Max to Min Gain)

AGC_T2

B

25

-

0.1

-

µS

Pre-Amp RF Output 1dB

Compression

VCC = 5.5V

PRE_P1DH

A

25, 85

6

8

-

dBm

RF Output Third Order Intercept

PRE_IP3

C

25

-

14

-

dBm

Input VSWR

PRE_ISWR

A

25, 85

1.0:1

2.0:1

3.0:1

-

Input Return Loss

PRE_IRL

A

25, 85

6

7

-

dB

Output VSWR

PRE_OSWR

A

25, 85

1.0:1

1.28:1

2.3:1

-

Output Return Loss

PRE_ORL

A

25, 85

8.09

20

-

dB

POWER SUPPLY AND LOGIC CHARACTERISTICS

Voltage Supply Range

VCC

A

25, 85

-

5.5

-

V

Supply Current (VCC = 5.5V)

ICC HI

A

25, 85

90

103

110

mA

ICC HIT

C

Full

-

-

110

mA

Power Down Supply Current (VCC = 5.5V)

ICC_PD

A

25, 85

2

3.3

4

mA

Logic Input Low Level

VIL

A

25, 85

-0.2

-

0.8

V

Logic Input High Level

VIH

A

25, 85

2.0

-

VCC

V

Logic Low Input Bias Current

(VPE = 0V, VCC = 5.5V)

IB_LO

A

25, 85

-5

-0.1

5

µA

Logic High Input Bias Current

(VPE = 5.5V, VCC = 5.5V)

IB_HI

A

25, 85

-5

0.6

5

µA

Vagc High Input Bias Current

(Vagc = 2.1V, VCC = 5.5V)

Ivagc_HI

A

25, 85

10

200

400

µA

Vagc Low Input Bias Current

(Vagc = 0.7V, VCC = 5.5V)

Ivagc_LO

A

25, 85

-400

-235

-10

µA

Power Enable Time (50% VPE to 90% ICC)

PEt

B

25

-

5

10

µs

Power Disable Time (50% VPE to 10% ICC)

PDt

B

25

-

0.1

10

µs

NOTES:

2. Test Level: A = 100% production tested, B = Typical or Limit based on characterization data, C = Design information, goal or condition.

3. Bias Resistor at pin 16 changes according to the relationship mentioned in Note 4 of the Typical Applications Circuit.

4-4

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