33976 查看數據表（PDF） - Freescale Semiconductor
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33976 Datasheet PDF : 41 Pages
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ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 4.75 V ≤ VDD ≤ 5.25 V, - 40°C ≤ TJ ≤ 150°C, GND = 0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Units
SPI INTERFACE TIMING (17)
Recommended Frequency of SPI Operation
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) (18)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) (18)
SI to Falling Edge of SCLK (Required Setup Time) (18)
Required High State Duration of SCLK (Required Setup Time (18)
Required Low State Duration of SCLK (Required Setup Time (18)
Falling Edge of SCLK to SI (Required Hold Time) (18)
SO Rise Time
CL = 200 pF
fSPI
–
tLEAD
–
tLAG
–
tSISU
–
tWSCLKH
–
tWSCLKL
–
tSI (HOLD)
–
tRSO
–
1.0
2.0
50
167
50
167
25
83
–
167
–
167
25
83
25
50
MHz
ns
ns
ns
ns
ns
ns
ns
SO Fall Time
CL = 200 pF
tFSO
ns
–
25
50
SI, CS, SCLK, Incoming Signal Rise Time (19)
tRSI
–
–
50
ns
SI, CS, SCLK, Incoming Signal Fall Time (19)
tFSI
–
–
50
ns
Falling Edge of RST to Rising Edge of RST (Required Setup Time) (18)
tWRST
–
–
3.0
µs
Rising Edge of CS to Falling Edge of CS (Required Setup Time) (18), (20)
t CS
–
–
5.0
µs
Rising Edge of RST to Falling Edge of CS (Required Setup Time) (18)
tEN
–
–
5.0
µs
Time from Falling Edge of CS to SO Low Impedance (21)
tSO(EN)
–
–
145
ns
Time from Rising Edge of CS to SO High Impedance (22)
tSO(DIS)
–
1.3
4.0
µs
Time from Rising Edge of SCLK to SO Data Valid (23)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
tVALID
ns
–
90
150
Notes
17. The 33976 shall meet all SPI interface timing requirements specified in the SPI Interface Timing section of this table, over the specified
temperature range. Digital interface timing is based on a symmetrical 50 percent duty cycle SCLK Clock Period of 333 ns. The device
shall be fully functional for slower clock speeds. Reference Figure 4 and 5.
18. The maximum setup time specified for the 33976 is the minimum time needed from the microcontroller to guarantee correct operation.
19. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
20. The value is for a 1.0 MHz calibrated internal clock. The value will change proportionally as the internal clock frequency changes.
21. Time required for output status data to be terminated at SO. 1.0 kΩ load on SO
22. Time required for output status data to be available for use at SO. 1.0 kΩ load on SO.
23. Time required to obtain valid data out from SO following the rise of SCLK.
33976
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
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