MSK4322S 查看數據表（PDF） - M.S. Kennedy
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MSK4322S Datasheet PDF : 6 Pages
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APPLICATION NOTES
MSK 4322 PIN DESCRIPTION
VCC - Is the low voltage supply for all the internal logic
and drivers. A 0.1 µF ceramic capacitor in parallel with
a 10µF tantalum capacitor is recommended bypassing
for the VCC-VSS pins.
VSS - Is the low voltage supply return pin and the input
logic return reference. All logic input and logic output
is referenced to this pin. This pin can vary ±5V from
the COM power return pin without affecting any of the
logic functions.
AØHIN, BØHIN, CØHIN - Are low active logic inputs for
signalling the corresponding phase high-side switch to
turn on. The input levels are 5V CMOS or TTL compat-
ible. Typical propagation delays are around 600nS.
AØLIN, BØLIN, CØLIN - Are low active inputs for sig-
nalling the corresponding phase low-side switch to turn
on. The input levels are 5V CMOS or TTL compatible.
Typical propagation delays are around 600nS.
FAULT - Is an open drain logic output pin that gets
enabled any time the VCC level goes below the cutoff
point, or an overcurrent condition occurs. Bringing VCC
back to normal levels will reset FAULT. Removing the
overcurrent condition and allowing the low-side logic
inputs to remain high(off) for 10µS will restore opera-
tion.
ITRIP - Is an analog input pin for sensing current flow-
ing from the COM pin through a sense resistor to the
high power ground. A 0.485 volt level at this pin with
respect to VSS will signal an overcurrent condition,
enable the FAULT pin and shut down all output switch-
ing. Bringing the voltage below this point (100 mV
hysteresis) will remove the FAULT output and leaving
the low-side logic inputs simultaneously high (de-acti-
vated) for 10µS will restore normal operation.
V+ - Is the high voltage positive rail for the bridge.
Proper bypassing to VSS with sufficient capacitance to
suppress any voltage transients and to ensure remov-
ing any drooping during switching, should be done as
close to the pins on the hybrid as possible.
COM - Is the return side of the bridge. A sense resistor
can be connected between this point and VSS, which
is the high voltage negative rail. COM can float above
and below the VSS pin up to 5 volts and proper opera-
tion will be maintained. Precautions should be taken
so as to not allow this voltage to get over ±5 volts
under any conditions.
AØ, BØ, CØ - Are the pins connecting the 3 phase
bridge switch outputs.
PROTECTION
- All logic inputs use a 300nS filter. A pulse width
below this will get ignored.
- VCC voltage below the cutoff level of 8.65 volts
will reset all switch outputs off and ignore subse-
quent logic inputs until VCC is restored.
- Undervoltage lockout of the internal drivers for the
high-side switches also occurs at 8.65 volts, but will
not flag with the FAULT output. This may occur if
the high-side output gets switched without switch
ing the low-side. The internal boot strap power
supply for the high-side switch will sag too low for
adequate switching. The boot strap supply depends
on PWMing of the low-side switches for proper
operation.
- Switching a low-side logic input while the corre-
sponding phase high-side logic input is activated
will turn off both switches. The opposite condition
is also true. This is cross-conduction lockout and
will occur any time low and high-side inputs for a
phase are activated at the same time.
- A 2µS deadtime is automatically inserted between
high and low-side output switching to allow com-
plete turn-off of each switch so no overlap will
occur.
- An overcurrent condition detected by the ITRIP
pin will shut down all output switches until the
overcurrent condition is removed and all three
low-side logic inputs are held high for 10µS,
then normal operation will resume.
- ITRIP has a 100nS leading edge blanking time
after switching to ignore any switching current
transients.
TYPICAL OPERATION
4
PRELIMINARY Rev. A 6/00
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