SN74LS196 查看數據表（PDF） - Motorola => Freescale
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SN74LS196 Datasheet PDF : 6 Pages
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SN54/74LS196 • SN54/74LS197
AC CHARACTERISTICS (TA = 25°C)
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Parameter
Maximum Clock Frequency
CP0 Input to
Q0 Output
CP1 Input to
Q1 Output
CP1 Input to
Q2 Output
CP1 Input to
Q3 Output
Data to Output
PL Input to
Any Output
MR Input to Any Output
AC SETUP REQUIREMENTS (TA = 25°C)
Symbol
tW
tW
tW
tW
ts
ts
th
th
trec
Parameter
CP0 Pulse Width
CP1 Pulse Width
PL Pulse Width
MR Pulse Width
Data Input Setup Time — HIGH
Data Input Setup Time — LOW
Data Hold Time — HIGH
Data Hold Time — LOW
Recovery Time
Limits
LS196
LS197
Min Typ Max Min Typ Max
30
40
30
40
8.0
15
13
20
8.0 15
14
21
16
24
22
33
12
19
23
35
38
57
41
62
34
51
42
63
12
18
30
45
55
78
63
95
20
30
29
44
18
27
29
44
27
41
30
45
26
39
30
45
34
51
34
51
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
Limits
LS196
Min Typ Max
LS197
Min Typ Max Unit
20
20
ns
30
30
ns
20
20
ns
15
15
ns
10
10
ns
15
15
ns
10
10
ns
10
10
ns
30
30
ns
Test Conditions
VCC = 5.0 V
CL = 15 pF
Test Conditions
VCC = 5.0 V
DEFINITIONS OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from HIGH to LOW in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from HIGH to LOW that the logic level must
be maintained at the input in order to ensure continued recog-
nition. A negative HOLD TIME indicates that the correct logic
level may be released prior to the clock transition from HIGH to
LOW and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from HIGH to LOW in order to recognize and transfer
LOW Data to the Q outputs.
FAST AND LS TTL DATA
5-5
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