AM29LV001BB-70EEB 查看數據表（PDF） - Advanced Micro Devices

零件编号

产品描述 (功能)

生产厂家

AM29LV001BB-70EEB

1 Megabit (128 K x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

GENERAL DESCRIPTION

The Am29LV001B is a 1 Mbit, 3.0 Volt-only Flash

memory device organized as 131,072 bytes. The

Am29LV001B has a boot sector architecture.

The device is offered in 32-pin PLCC and 32-pin TSOP

packages. The byte-wide (x8) data appears on DQ7-DQ0.

All read, erase, and program operations are accomplished

using only a single power supply. The device can also be

programmed in standard EPROM programmers.

The standard Am29LV001B offers access times of 45,

55, 70, and 90 ns, allowing high speed microprocessors

to operate without wait states. To eliminate bus contention,

the device has separate chip enable (CE#), write enable

(WE#) and output enable (OE#) controls.

The device requires only a single power supply (2.7 V–3.6V)

for both read and write functions. Internally generated and

regulated voltages are provided for the program and

erase operations.

The Am29LV001B is entirely command set compatible

with the JEDEC single-power-supply Flash stan-

dard. Commands are written to the command register

using standard microprocessor write timings. Register

contents serve as input to an internal state-machine

that controls the erase and programming circuitry.

Write cycles also internally latch addresses and data

needed for the programming and erase operations.

Reading data out of the device is similar to reading

from other Flash or EPROM devices.

Device programming occurs by executing the program

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that automati-

cally times the program pulse widths and verifies proper cell

margin. The Unlock Bypass mode facilitates faster pro-

gramming times by requiring only two write cycles to

program data instead of four.

Device erasure occurs by executing the erase command

sequence. This initiates the Embedded Erase algo-

rithm—an internal algorithm that automatically preprograms

the array (if it is not already programmed) before executing

the erase operation. During erase, the device automatically

times the erase pulse widths and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits. After a program

or erase cycle has been completed, the device is ready

to read array data or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low VCC

detector that automatically inhibits write operations during

power transitions. The hardware sector protection

feature disables both program and erase operations in

any combination of the sectors of memory. This can be

achieved in-system or via programming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. True background erase can thus be achieved.

The hardware RESET# pin terminates any operation

in progress and resets the internal state machine to

reading array data. The RESET# pin may be tied to the

system reset circuitry. A system reset would thus also

reset the device, enabling the system microprocessor

to read the boot-up firmware from the Flash memory.

The device offers two power-saving features. When

addresses have been stable for a specified amount of time,

the device enters the automatic sleep mode. The system

can also place the device into the standby mode. Power

consumption is greatly reduced in both these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the highest

levels of quality, reliability and cost effectiveness. The

device electrically erases all bits within a sector simulta-

neously via Fowler-Nordheim tunneling. The data is

programmed using hot electron injection.

2

Am29LV001B

September 26, 2002

Share Link: