56F805 查看數據表（PDF） - Motorola => Freescale

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56F805

16-bit Hybrid Controller

Motorola => Freescale 

Freescale Semiconductor, Inc.

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F805 are organized into functional groups, as shown in Table 2 and

as illustrated in Figure 2. In Table 3 through Table 19, each table row describes the signal or signals

present on a pin.

Table 2. Functional Group Pin Allocations

Functional Group

Number of

Pins

Detailed

Description

Power (VDD or VDDA)

Ground (VSS or VSSA)

Supply Capacitors and VPP

PLL and Clock

Address Bus1

Data Bus

Bus Control

Interrupt and Program Control

Dedicated General Purpose Input/Output

Pulse Width Modulator (PWM) Port

Serial Peripheral Interface (SPI) Port1

Quadrature Decoder Port2

Serial Communications Interface (SCI) Port1

CAN Port

Analog to Digital Converter (ADC) Port

Quad Timer Module Ports

JTAG/On-Chip Emulation (OnCE)

1. Alternately, GPIO pins

2. Alternately, Quad Timer pins

9

Table 3

9

Table 4

3

Table 5

3

Table 2.3

16

Table 7

16

Table 8

4

Table 9

5

Table 10

14

Table 11

26

Table 12

4

Table 13

8

Table 14

4

Table 15

2

Table 16

9

Table 17

6

Table 18

6

Table 19

6

56F805 Technical Data

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