56F805 查看數據表（PDF） - Motorola => Freescale
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56F805 Datasheet PDF : 48 Pages
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Freescale Semiconductor, Inc.
Address, Data, and Bus Control Signals
Table 6. PLL and Clock (Continued)
No. of Signal Signal State During
Pins Name Type
Reset
Signal Description
1
CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
2.4 Address, Data, and Bus Control Signals
Table 7. Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5 Output
Tri-stated
Address Bus—A0–A5 specify the address for external
Program or Data memory accesses.
2
A6–A7 Output
Tri-stated
Address Bus—A6–A7 specify the address for external
Program or Data memory accesses.
Input
GPIOE2– Input/
Port E GPIO—These two General Purpose I/O (GPIO) pins
GPIOE3 Output
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15 Output
Tri-stated
Address Bus—A8–A15 specify the address for external
Program or Data memory accesses.
Input
GPIOA0– Input/
Port A GPIO—These eight General Purpose I/O (GPIO) pins
GPIOA7 Output
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
Table 8. Data Bus Signals
No. of
Pins
Signal
Name
Signal State During
Type
Reset
Signal Description
16 D0–D15 Input/
Tri-stated Data Bus— D0–D15 specify the data for external Program or
Output
Data memory accesses. D0–D15 are tri-stated when the external
bus is inactive. Internal pullups may be active.
56F805 Technical Data
9
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