MC56F8033/56F8023 查看數據表（PDF） - Freescale Semiconductor
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MC56F8033/56F8023 Datasheet PDF : 157 Pages
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2 and 3 outputs are connected to the ADC sync inputs. Timer Channel 3 output is connected to SYNC0
and Timer Channel 2 is connected to SYNC1. These are controlled by bits in the SIM Control Register;
see Section 6.3.1.
DSP56800E Core
Program Control Unit
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
LC
LC2
FISR
Instruction
Decoder
Interrupt
Unit
Looping
Unit
Address
Generation
Unit
(AGU)
M01
N3
ALU1
ALU2
R0
R1
R2
R3
R4
R5
N
SP
XAB1
XAB2
PAB
PDB
CDBW
CDBR
XDB2
Bit-
Manipulation
Unit
Enhanced
OnCE™
JTAG TAP
A2
A1
B2
B1
C2
C1
D2
D1
Y1
Y
Y0
X0
A0
B0
C0
D0
Data
Arithmetic
Logic Unit
(ALU)
MAC and ALU Multi-Bit Shifter
Program
Memory
Data /
Program
RAM
IPBUS
Interface
Figure 1-1 56800E Core Block Diagram
56F8033/56F8023 Data Sheet, Rev. 6
10
Freescale Semiconductor
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