DSP56F805 查看數據表（PDF） - Freescale Semiconductor

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DSP56F805

16-bit Digital Signal Controllers

Freescale Semiconductor 

2.14 JTAG/OnCE

JTAG/OnCE

Table 2-18 JTAG/On-Chip Emulation (OnCE) Signals

No. of Signal Signal State During

Pins Name Type

Reset

Signal Description

1

TCK Input Input, pulled Test Clock Input—This input pin provides a gated clock to

(Schmitt) low internally synchronize the test logic and shift serial data to the JTAG/OnCE

port. The pin is connected internally to a pull-down resistor.

1

TMS Input Input, pulled Test Mode Select Input—This input pin is used to sequence the

(Schmitt) high internally JTAG TAP controller’s state machine. It is sampled on the rising

edge of TCK and has an on-chip pull-up resistor.

Note: Always tie the TMS pin to VDD through a 2.2K resistor.

1

TDI

Input Input, pulled Test Data Input—This input pin provides a serial input data stream

(Schmitt) high internally to the JTAG/OnCE port. It is sampled on the rising edge of TCK and

has an on-chip pull-up resistor.

1

TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial

output data stream from the JTAG/OnCE port. It is driven in the

Shift-IR and Shift-DR controller states, and changes on the falling

edge of TCK.

1

TRST Input Input, pulled Test Reset—As an input, a low signal on this pin provides a reset

(Schmitt) high internally signal to the JTAG TAP controller. To ensure complete hardware

reset, TRST should be asserted at power-up and whenever RESET

is asserted. The only exception occurs in a debugging environment

when a hardware device reset is required and it is necessary not to

reset the OnCE/JTAG module. In this case, assert RESET, but do

not assert TRST.

Note: For normal operation, connect TRST directly to VSS. If the design

is to be used in a debugging environment, TRST may be tied to VSS

through a 1K resistor.

1

DE Output

Output Debug Event—DE provides a low pulse on recognized debug

events.

Part 3 Specifications

3.1 General Characteristics

The 56F805 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term

“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to

withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices

designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible

I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during

56F805 Technical Data, Rev. 15

Freescale Semiconductor

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